Abstract: A method and system for enhancing the efficiency of the completion of host-initiated I/O operations within a fiber channel node. The host computer component of the fiber channel node does not allocate the memory buffer for the FCP response frame received by the FC node at the completion of an I/O operation. Instead, the interface controller of the FC node processes FCP response frames in order to determine whether or not an I/O operation successfully completes. In the common case that the I/O operation successfully completes, the interface controller writes the FCP exchange ID corresponding to the I/O operation to a special location in memory which serves to invoke logic functions implemented in an ASIC that de-allocate host memory resources allocated for the I/O operation.

Abstract: A FC controller that interfaces between a host system and a 10-bit FC interface is herein described. The FC controller acts as both a FCP initiator and FCP target device and has the capability to receive and process SCSI I/O requests received from a FC and a host system. The FC controller can process both multiple inbound and outbound sequences simultaneously since it does not employ a processor-based architecture. Rather, the FC controller relies on specialized circuitry that can operate in a relatively independent manner so that multiple tasks are performed concurrently thereby achieving a faster throughput and data transfer rate.

Abstract: An interface controller used within communications network ports that can be deterministically shut down by a host processor within a communication node that includes the communications network port and that can shut itself down in an ordered and deterministic manner in response to detection of certain error conditions. The interface controller purges any commands and information stored within internal caches, carries forward any currently executed operations to reasonable halting points, and finally provides complete control of data structures shared by the interface controller and the host processor to the host processor.

Abstract: A method and system, implemented in hardware, for quickly and efficiently reassembling Fibre Channel data sequence data received by a Fibre Channel port in host memory buffers. The host memory buffers are referenced by a transaction status block allocated and initialized by the host. The transaction status block is referenced by the Fibre Channel port during transfer of data received in each Fibre Channel data frame of the Fibre Channel data sequence. The host memory buffers may be or arbitrary size and need only be byte aligned. The host computer can specify any number of host memory buffers by appropriate initialization of the transaction status block.

Abstract: A one stage first-in-first-out synchronizer includes a producer side and a consumer side. The producer side includes a first write buffer, a not full output, a write input, a second write buffer and a write clock input. The first write buffer stores a write pointer. The not full output indicates whether new data may be written. The write input is asserted to write data. The second write buffer receives as input a read pointer. The write clock input is used to provide a clock signal to the first write buffer and the second write buffer. The consumer side includes a first read buffer, a not empty output, a read input, a second read buffer, and a read clock input. The first read buffer stores the read pointer. The not empty output indicates whether stored data may be read. The read input is asserted to read data. The second read buffer receives as input the write pointer. The read clock input is used to provide a clock signal to the first write buffer and the second write buffer.

Abstract: An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of said first memory means for storing data, and a third memory for storing data connected to the output of said second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the `not full` signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.

Abstract: An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of the first memory means for storing data, and a third memory for storing data connected to the output of the second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the `not full` signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.