Abstract: A method and disk drive for calibrating a phase of a clock in the disk drive. The phase of the clock in the disk drive is changed such that a rate of change for the phase is substantially constant. A pattern of data is written to a magnetic material in the disk drive after the rate of change for the phase becomes substantially constant and while changing the phase of the clock. A selected phase of the clock at which the pattern of data that is written on the magnetic material has a desired quality is identified using the rate of change for the phase, a first point in time at which a timing mark on the magnetic material is read, a second point in time at which the timing mark is read, and a third point in time at which the pattern of data has the desired quality.

Abstract: The invention provides a simulation task generator that receives a range of parameters that are desired for a particular parallel simulation. The simulation task generator determines specific combinations of parameters which corresponds to each simulation task and assigns estimated performance ratings for each of the simulation tasks. The simulation task generator retrieves information from a database that indicates availability of accessible processors and ratings corresponding to each of the accessible processors. The simulation task generator matches the simulation tasks to the available processors to achieve an optimum performance. Some of the available processors may also be used as secondary distributors. Such processors may be provided subranges of the parameters and generate simulation tasks and distribute those tasks to other processors more conveniently accessed by the secondary distributor.

Abstract: A four-quadrant mixer is disclosed which has a low noise factor. The indeterminate common-mode voltage that may accompany the modulating signal is suppressed and replaced by a common-mode quiescent voltage designed to establish a predetermined quiescent biasing current through the mixer transistors common biasing resistors so that the mixer may be driven in common-mode by the modulating signal and differentially by the local oscillator signal. Advantageously, a larger value emitter biasing resistor can be used with the same value of emitter current that would obtain in a comparable four-quadrant Gilbert Mixer or, conversely, larger values of emitter current can be specified to establish a desired level of signal to noise ratio.

Abstract: The invention provides for a system and method for performing parallel simulations. The system includes a plurality of processors separated into groups and locating the groups in mutually exclusive time zones. Processors of one time zone may be use processors of other time zones for parallel simulation tasks. The system also includes a network that couples the plurality of processors together. Thus, simulation tasks may be assigned and transmitted by any processor to any other processor via the network. The system may also include a parallel simulation coordination device which includes a memory, a controller, a network interface and a database interface. The parallel simulation coordination device may receive calls from callers that wish to register a processor to make the processor available for parallel simulation or calls to request a parallel simulation job. The parallel simulation coordination device authorizes the parallel simulation job bills the caller for performing the parallel simulation.

Abstract: This invention provides a phase splitter device that generates in-phase and quadrature outputs that have a phase difference of substantially a phase set value (e.g., 90°) and an amplitude difference of substantially an amplitude set value (e.g., zero). A first feedback loop controls the phase difference between the in-phase and the quadrature outputs while a second feedback loop controls the amplitude difference between the in-phase and quadrature outputs. The phase splitter device controls the amplitude difference and the phase difference between the in-phase and the quadrature outputs by a common mode of control signals and a differential between the control signals, respectively. In this way, the phase splitter device generates in-phasing and quadrature outputs that have a phase difference and an amplitude difference that is substantially equal to the amplitude and phase set values (e.g., zero and 90°) using a single set of control signals.

Abstract: Correction of a duty-cycle is performed for use with a divide-by-two phase-splitter to increase precision of the duty-cycle of an incoming local oscillator signal in order to provide more precise phase relationships during generation of a phase and amplitude modulated carrier. Phase-splitter input signals are generated by limiting the slew-rate of an incoming signal to produce an intermediate signal. The intermediate signal is clipped in relation to a reference level. The reference level is adjusted by a feedback signal to produce an adjusted duty-cycle signal as an output signal. The feedback signal is proportional to the adjusted duty-cycle signal.