Abstract: Embodiments of the present invention provide functionality, within a storage-shelf-router integrated circuit, an I/O-controller integrated circuit, or other integrated-circuit implementations of complex electronic devices, for interconnecting all possible pairs of communications ports, a first member of each pair selected from a first set of communications ports and a second member of each pair selected from a second set of communications ports. Embodiments of the present invention employ a time-division-multiplexed global shared memory in order to provide full cross-communications between two or more sets of serial-communications ports, using modest controlling clock rates and wide data-transfer channels.

Abstract: Monitoring in switch networks is disclosed. Ports in a switch may include monitoring circuitry and a monitoring tap which allows traffic data to be diverted for monitoring prior to any significant transformation of the traffic by the regular port logic. Furthermore, the monitoring circuitry can receive signaling and convert it for subsequent analysis by a protocol analyzer. The ports and paths in the switch network can be configured to create monitor paths to enable diverted traffic data to be passed through the network to locations where a protocol analyzer can be easily attached. With wide bandwidth ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: Embodiments of the present invention provide for an IOC that does not limit each CPU to a particular port. Instead, the IOC may allow each CPU to communicate with all ports. Thus, the IOC can process CPU communications to determine which port to send them to, and send them to the correct port as well as process incoming communications from the ports to determine which CPU to send them to and send these communications to the correct CPU. This may significantly increase the flexibility and efficiency of a storage network.

Abstract: In one embodiment of the present invention, a two-register interface is provided by a first electronic device to allow access to memory within the electronic device by external electronic devices. The two-register interface is mapped from the memory of an accessing, second electronic device. READ and WRITE accesses are transmitted from the accessing, second electronic device to the two-register interface through a communications medium. A first register of the two-register interface directs access to a particular memory location, and the second register of the two-register interface provides a portal for both READ and WRITE access to the particular memory location.

Abstract: Disclosed herein is an improved sector remapping method that maps logical sectors into physical sectors in storage disks such as SATA (Serial ATA) drives without reducing either storage capacity or I/O performance efficiency. Under this sector remapping method, logical sectors of data can be written into the physical sectors of a storage device through control frames having padded data or information associated with the padded data, as well as data frames having real data to be stored. With the padded data to be added to the real data, the frames provide multiple physical sectors to be transmitted into the storage device in a single write operation. The sector remapping method can be implemented in a storage bridge coupled to a storage device such as SATA drives.

Abstract: One embodiment of the present invention is a virtual disk formatting system includes a mass-storage device having physical sectors that each contains a data payload of a first data length and additional information, including one or more of a sector number, error-detection, and error-correction information and a virtual disk interface to the mass-storage device, implemented in an integrated circuit, that maps access operations, received from external entities by the virtual disk interface, directed to a virtual disk having virtual sectors containing a data payload of a second data length by contiguously mapping an array of virtual-sector data payloads to a contiguous array of physical-sector data payloads without introducing padding data into physical-sector data payloads or into virtual-sector data payloads to align the initial bytes of virtual sectors and physical sectors.

Abstract: Embodiments of the present invention are directed to methods for efficient queue management, and device implementations that incorporate these methods, for systems that include two or more electronic devices that share a queue residing in the memory of one of the two or more electronic devices. In certain embodiments of the present invention, a discard field or bit is included in each queue entry. The bit or field is set to a first value, such as the Boolean value “0,” by a producing device to indicate that the entry is valid, or, in other words, that the entry can be consumed by the consuming device. After placing entries into the queue, the producing device may subsequently remove one or more entries from the queue by setting the discard field or bit to a second value, such as Boolean value “1.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. In various embodiments, the present invention provides virtual disk formatting by a storage shelf router and the storage shelf in which the storage-shelf is included, to external computing entities, such as disk-array controllers and host computers.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. In various embodiments, the present invention provides virtual disk formatting by a storage shelf router and the storage shelf in which the storage-shelf is included, to external computing entities, such as disk-array controllers and host computers.

Abstract: Embodiments of the present invention provide for an IOC that does not limit each CPU to a particular port. Instead, the IOC may allow each CPU to communicate with all ports. Thus, the IOC can process CPU communications to determine which port to send them to, and send them to the correct port as well as process incoming communications from the ports to determine which CPU to send them to and send these communications to the correct CPU. This may significantly increase the flexibility and efficiency of a storage network.

Abstract: Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop, through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. A set of interconnected storage-shelf routers within a storage shelf can be accessed through a single port of an FC arbitrated loop or other high-bandwidth communications medium. Because, in one implementation, eight storage-shelf routers can be interconnected within a storage shelf to provide highly available interconnection of sixty-four disk drives within the storage shelf to an FC arbitrated loop via a single FC-arbitrated-loop port, a single FC arbitrated loop including a disk-array controller, may interconnect 8,000 individual disk drives to the disk-array controller within a disk array.

Abstract: Embodiments of the present invention include a storage-shelf-router-to-disk-drive interconnection method within a high-availability storage shelf amenable to dynamic reorganization in order to ameliorate error conditions that arise within the high-availability storage shelf. In one embodiment, each path-controller card within the storage shelf is interconnected to two storage-shelf routers on separate storage-shelf-router cards via two serial management links and two serial data links. Different types of errors that may arise within the storage shelf are carefully classified with respect to a number of different error-handling techniques, including local path failovers, single path failovers, error reporting and logging, and other types of error handling techniques. In many implementations, particular error handling methods are conifigurably associated with particular errors, in order to adapt error behavior in a storage shelf to the needs and requirements of a system that includes the storage shelf.

Abstract: An integrated circuit implementing a storage-shelf router, used in combination with path controller cards and optionally with other storage-shelf routers, to interconnect SATA disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop. Various embodiments of the present invention provide a tunneling mechanism through the storage-shelf interface provided by one or more storage-shelf routers within a storage shelf to enable external processing entities to directly access various components within the storage shelf. In one embodiment of the present invention, a WRITE-BUFFER command and a READ-BUFFER command are added to the command interface supported by storage-shelf router. These commands are exchanged via the FCP protocol over the fiber channel in the same manner that SCSI commands are packaged within the FCP protocol.

Abstract: A method for replacing finite state machine hardware implementations of controllers and controller subcomponents with implementations based on manipulating contexts stored within common data structures, such as linked lists, and an outbound sequence manager subcomponent of a fibre channel interface controller implemented by this method. A state transition diagram is analyzed to define managers within the controller, along with commands received by, and generated by, each manager. Data structures are chosen for each manager to store contexts representing tasks currently operated on by the manager. An additional manger and interface are designed for a data-structure-manipulation manager. Finally, the operations performed by the managers are defined and implemented, with sequencing of operations controlled by transfer of contexts between data structures by the data-structure-manipulation manager.

Abstract: A method and system for non-blocking processing of data frames and link-control frames within an interface controller component of a fiber channel node. Separate FIFO queues are provided for queuing incoming FC data frames and ACK frames and a separate FIFO queue and list are provided for queuing outgoing FC data frames and buffering outgoing ACK frames. An outbound sequence manager component of the interface controller directly processes incoming ACK frames, transforming them into end-to-end credits that allow the outbound sequence manager to transmit additional FC data frames to the remote node that sent the processed ACK frame. Thus, processing of ACK frames, unlike in prior art interface controller implementations, is neither delayed nor blocked by previously received, but as yet unprocessed, FC data frames.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. In various embodiments, the present invention provides virtual disk formatting by a storage shelf router and the storage shelf in which the storage-shelf is included, to external computing entities, such as disk-array controllers and host computers.

Abstract: An integrated circuit implementing a storage-shelf router, used in combination with path controller cards and optionally with other storage-shelf routers, to interconnect SATA disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop. Various embodiments of the present invention provide a tunneling mechanism through the storage-shelf interface provided by one or more storage-shelf routers within a storage shelf to enable external processing entities to directly access various components within the storage shelf. In one embodiment of the present invention, a WRITE-BUFFER command and a READ-BUFFER command are added to the command interface supported by storage-shelf router. These commands are exchanged via the FCP protocol over the fiber channel in the same manner that SCSI commands are packaged within the FCP protocol.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop, through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. A set of interconnected storage-shelf routers within a storage shelf can be accessed through a single port of an FC arbitrated loop or other high-bandwidth communications medium. Because, in one implementation, eight storage-shelf routers can be interconnected within a storage shelf to provide highly available interconnection of sixty-four disk drives within the storage shelf to an FC arbitrated loop via a single FC-arbitrated-loop port, a single FC arbitrated loop including a disk-array controller, may interconnect 8,000 individual disk drives to the disk-array controller within a disk array.