Patents by Inventor Joseph Hasting
Joseph Hasting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200004584Abstract: In an embodiment, a processor for queue selection includes a plurality of processing engines (PEs) to execute threads, and a hardware queue manager. The hardware queue manager is to: detect that a first class lacks valid requests to be scheduled, the first class comprising a first plurality of scheduling queues, the first class associated with a first credit count; select a second class based on a second credit count associated with the second class, the second class comprising a second plurality of scheduling queues; and in response to a selection of the second class based on the second credit count, select a queue in the selected second class. Other embodiments are described and claimed.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: William Burroughs, James Clee, Ambalavanar Arulambalam, Joseph Hasting, Niall Mcdonnell
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Patent number: 10216668Abstract: Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.Type: GrantFiled: March 31, 2016Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew Herdrich, Tsung-Yuan Tai, Niall McDonnell, Stephen Van Doren, David Sonnier, Debra Bernstein, Hugh Wilkinson, Narender Vangati, Stephen Miller, Gage Eads, Andrew Cunningham, Jonathan Kenny, Bruce Richardson, William Burroughs, Joseph Hasting, An Yan, James Clee, Te Ma, Jerry Pirog, Jamison Whitesell
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Publication number: 20170286337Abstract: Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew Herdrich, Tsung-Yuan Tai, Niall McDonnell, Stephen Van Doren, David Sonnier, Debra Bernstein, Hugh Wilkinson, Narender Vangati, Stephen Miller, Gage Eads, Andrew Cunningham, Jonathan Kenny, Bruce Richardson, William Burroughs, Joseph Hasting, An Yan, James Clee, Te Ma, Jerry Pirog, Jamison Whitesell
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Patent number: 8677075Abstract: Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.Type: GrantFiled: January 27, 2012Date of Patent: March 18, 2014Assignee: LSI CorporationInventors: Deepak Mital, William Burroughs, David Sonnier, Steven Pollock, David Brown, Joseph Hasting
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Patent number: 8499137Abstract: Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result.Type: GrantFiled: December 9, 2010Date of Patent: July 30, 2013Assignee: LSI CorporationInventors: Joseph Hasting, Deepak Mital
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Publication number: 20120131283Abstract: Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Inventors: Deepak Mital, William Burroughs, David Sonnier, Steven Pollock, David Brown, Joseph Hasting
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Publication number: 20110225376Abstract: Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result.Type: ApplicationFiled: December 9, 2010Publication date: September 15, 2011Inventors: Joseph Hasting, Deepak Mital
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Patent number: 6349666Abstract: An articulated boat top assembly is attached to a conventional boat and operable to be moved between an extended position and a retracted position. The articulated boat top assembly includes a boat top that is secured to the boat via two articulated frame members. The articulated frame members include a series of skeletal components that are pivotally connected to each other. The skeletal components of the articulated boat top assembly include a base member, a pair of middle arms, and a pair of upper arms. The base member includes a pair of legs rigidly attached to the boat deck. The legs of the base member are additionally connected to each other via a stabilizing arm that reinforces the position of the frame members.Type: GrantFiled: March 7, 2001Date of Patent: February 26, 2002Inventor: Joseph A. Hastings
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Patent number: 5068085Abstract: A sterilizer for medical or dental instruments utilizes a reservoir of reusable heat transfer beads, a preselected quantity of which are released into an instrument tray containing instruments to be sterilized. The tray and beads are positioned within a heating column for sterilization and the tray with beads is thereafter removed to the top of the column for instant utilization. The beads are released through the bottom of the tray into the reservoir for reheating.Type: GrantFiled: October 17, 1988Date of Patent: November 26, 1991Inventor: Joseph A. Hastings