Abstract: A method of controlling a spectral property of a light beam includes directing a light beam to a lithography exposure apparatus configured to create a pattern on a wafer; receiving information representative of a spectral property of the light beam; receiving information representative of an optical imaging condition of the lithography exposure apparatus; estimating a characteristic value of the light beam based on the received spectral property information and the received optical imaging condition information; determining whether the estimated light beam characteristic value matches a target light beam characteristic value; and if it is determined that the estimated light beam characteristic value does not match the target light beam characteristic value, adjusting the spectral property of the light beam.

Abstract: A method of controlling a spectral property of a light beam includes directing a light beam to a lithography exposure apparatus configured to create a pattern on a wafer; receiving information representative of a spectral property of the light beam; receiving information representative of an optical imaging condition of the lithography exposure apparatus; estimating a characteristic value of the light beam based on the received spectral property information and the received optical imaging condition information; determining whether the estimated light beam characteristic value matches a target light beam characteristic value; and if it is determined that the estimated light beam characteristic value does not match the target light beam characteristic value, adjusting the spectral property of the light beam.

Abstract: A method and apparatus for embedded encoding of overlay data ordering in an in-situ interferometer is described. An in-situ interferometer is encoded, or augmented, with special or missing alignment attributes at desired positions. Exposing a sequence of the encoded in-situ interferometer onto a silicon wafer coated with a suitable recording media. Then measuring the alignment attributes. The encoded overlay data is processed to verify the proper order and physical location of each overlay measurement. The data is collected without increasing the overall number of required overlay measurements required. Collection of overlay data allows for the proper reconstruction of the aberrated wavefront. Non-coupling alignment attribute offsets can also be used to perform similar operations using singular value decomposition and null space operations.

Abstract: A method for controlling the variation in process parameters using test structures sensitized to process parameter changes. Wavefront engineering techniques are used to make features of the test structure more sensitive to process changes. Focus and exposure parameters are adjusted in response to the measurements of the test structures. In another embodiment, the wavefront engineering features are placed to permit the test structure appearing on the reticle out of focus. The wavefront engineering feature is an OPC technique applied to the test structure to modify it. The OPC features are applied in an asymmetrical manner to the test structure and enable identifying the direction of process focus changes.

Abstract: The present invention provides a “built-in” wave dampening, antireflective thin-film layer in a copper dual damascene film stack that reduces the standing wave intensity in the deep-UV photoresist. This is accomplished by depositing optically customized silicon/oxide/nitride films during dual damascene processing. In particular, one or more silicon nitride layers are replaced with a light absorbing silicon oxynitride film to provide built-in dampening layers. The silicon oxynitride stack can be densified by heat treatments to minimize electrical leakage concerns, if any. The invention eliminates the need for adding extra thin-film stacks during deep-UV photoprocessing.

Abstract: A microelectronic device is fabricated by furnishing a first substrate (40) having a silicon etchable layer (42), a silicon dioxide etch-stop layer (44) overlying the silicon layer (42), and a single-crystal silicon wafer (46) overlying the etch-stop layer (44), the wafer (46) having a front surface (52) not contacting the etch stop layer (44). A microelectronic circuit element (50) is formed in the single-crystal silicon wafer (46). The method further includes attaching the front surface (52) of the single-crystal silicon wafer (46) to a second substrate (58), and etching away the silicon layer (42) of the first substrate (40) down to the etch-stop layer (44). The second substrate (58) may also have a microelectronic circuit element (58') therein that can be electrically interconnected to the microelectronic circuit element (50).

Abstract: A microelectronic device is fabricated on a first substrate (40), and transferred to a second substrate (58). The first substrate (40) has a silicon etchable layer (42), a silicon dioxide etch-stop layer (44) overlying the etchable layer (42), and a single-crystal wafer (46) overlying the etch-stop layer (44). A microelectronic circuit element (48) is formed in the wafer (46) of the first substrate (40). The wafer (46) of the first substrate (40) is attached to an aluminum oxide temporary substrate (52), and the etchable layer (42) of the first substrate (40) is etched away down to the etch-stop layer (44) to leave a primary device structure. The etch-stop layer (44) may optionally be processed to remove all or a part of the layer. An exposed surface (56) of the primary device structure is fixed to the second substrate (58), and the temporary substrate (52) is removed.

Abstract: An improved silicon chip metallization system for use in attaching silicon chips to substrates. The improvement comprises providing a layer of titanium between the silicon chip backside and the layers of chrome and gold which are conventionally used as the backside metallization. The layer of titanium adjacent to the silicon chip backside reduces silicon dioxide formation during chip attachment procedures carried out in non-vacuum environments.