Abstract: A tape device adapter logic control system is disclosed for accommodating the transfer of control information and data of variable formats, densities, and logic level conventions between a medium performance device controller (MPDC) and mass storage devices. Information recorded in one processor code may be converted for use in a data processor having any other processor code, and may be packed or depacked to accommodate a change in density. Tristate logic is used to provide recursive data paths, thereby accommodating plural functions with minimal duplication of logic devices.The MPDC loads control information into a device command register and an adapter command register of the tape device adapter to respectively provide control commands to device controllers and to the logic control system. The adapter command register controls the data flow through the tape adapter, and the operation of logic devices in the flow path to effect a 1.times.1, 4.times.3, 8.times.5, or 8.times.

Abstract: A hardware logic timing system for a tape device adapter is disclosed for accommodating the exchange of control information and data between a medium performance device controller (MPDC) and mass storage devices. Plural timing frequencies exhibiting selectively variable phase relationships are provided for increased operating mode flexibility. More particularly, 1.times.1, 4.times.3, 8.times.5, 8.times.7 or 8.times.9 data packing or depacking operations with or without code conversion are supported during both data reads and data writes.The logic timing system is responsive to the MPDC and each of the mass storage devices, and may operate in clear, wait, normal or burst modes to preserve information integrity while maintaining commercially acceptable transfer rates.