Patents by Inventor Joseph L. Petrucci

Joseph L. Petrucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6900105
    Abstract: In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) is formed on a silicon substrate layer (101) with an epitaxial layer (203). Trenches (233) are cut into the epitaxial layer (203) and filled with oxide (601) to provide reduced junction capacitance and reduced base resistance. The emitter region (211) and the base enhancement region (207) are simultaneously formed through an anneal process.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: May 31, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John L. Freeman, Jr., Raymond J. Balda, Robert A. Pryor, Joseph L. Petrucci, Jr., Robert J. Johnsen
  • Publication number: 20020190351
    Abstract: In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) is formed on a silicon substrate layer (101) with an epitaxial layer (203). Trenches (233) are cut into the epitaxial layer (203) and filled with oxide (601) to provide reduced junction capacitance and reduced base resistance. The emitter region (211) and the base enhancement region (207) are simultaneously formed through an anneal process.
    Type: Application
    Filed: August 2, 2002
    Publication date: December 19, 2002
    Inventors: John L. Freeman, Raymond J. Balda, Robert A. Pryor, Joseph L. Petrucci, Robert J. Johnsen