Patents by Inventor Joseph L. Sousa

Joseph L. Sousa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11754599
    Abstract: A measurement circuit comprises an input terminal to receive a current signal, a first circuit branch coupled to the first terminal and including one or more circuit elements to receive a portion of the current signal, a second circuit branch coupled to the first terminal and including one or more additional circuit elements to receive another portion of the current signal, a nonlinear circuit element coupling the first circuit branch to the second circuit branch, and a quantization circuit configured to produce an input current measurement of current in the first and second circuit branches, and to include current in the second circuit branch in the input current measurement according to a magnitude of the input current signal.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: September 12, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Andrew Joseph Thomas, Joseph L. Sousa, Micah Galletta O'Halloran, Alex Robert Sloboda
  • Publication number: 20230013695
    Abstract: A measurement circuit comprises an input terminal to receive a current signal, a first circuit branch coupled to the first terminal and including one or more circuit elements to receive a portion of the current signal, a second circuit branch coupled to the first terminal and including one or more additional circuit elements to receive another portion of the current signal, a nonlinear circuit element coupling the first circuit branch to the second circuit branch, and a quantization circuit configured to produce an input current measurement of current in the first and second circuit branches, and to include current in the second circuit branch in the input current measurement according to a magnitude of the input current signal.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Inventors: Andrew Joseph Thomas, Joseph L. Sousa, Micah Galletta O'Halloran, Alex Robert Sloboda
  • Patent number: 11428719
    Abstract: A measurement circuit comprises an electronic circuit, multiple measurement channels, and a combining circuit. The electronic circuit includes a first terminal, a second terminal, and a non-resistive circuit element. Each of the multiple measurement channels includes a differential input connected to the electronic circuit. The differential inputs of the multiple measurement channels are connected in series and include a differential input coupled to the non-resistive circuit element. One input of a differential input of a first measurement channel of the multiple measurement channels is connected to the first terminal of the electronic circuit and one input of a differential input of a second measurement channel of the multiple measurement channels is connected to the second terminal of the electronic circuit. The combining circuit receives multiple outputs from the multiple measurement channels and produce a composite output signal.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 30, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Joseph L. Sousa, Micah Galletta O'Halloran, Andrew Joseph Thomas
  • Patent number: 11095254
    Abstract: A device to reduce distortion in an amplifier includes an input transistor configured to generate a voltage based on an input signal. The device further includes a diode connected transistor that is configured to sink the current. The diode connected transistor includes an output terminal, and a control terminal, where the output terminal is coupled to a control terminal. The device further includes a current source circuit that coupled to the control terminal. The device additionally includes an impedance element that coupled to the output terminal at a first node and to the control terminal and the current source circuit at a second node.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 17, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventor: Joseph L. Sousa
  • Publication number: 20210234514
    Abstract: A device to reduce distortion in an amplifier includes an input transistor configured to generate a voltage based on an input signal. The device further includes a diode connected transistor that is configured to sink the current. The diode connected transistor includes an output terminal, and a control terminal, where the output terminal is coupled to a control terminal. The device further includes a current source circuit that coupled to the control terminal. The device additionally includes an impedance element that coupled to the output terminal at a first node and to the control terminal and the current source circuit at a second node.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 29, 2021
    Inventor: Joseph L. Sousa
  • Publication number: 20210215745
    Abstract: A measurement circuit comprises an electronic circuit, multiple measurement channels, and a combining circuit. The electronic circuit includes a first terminal, a second terminal, and a non-resistive circuit element. Each of the multiple measurement channels includes a differential input connected to the electronic circuit. The differential inputs of the multiple measurement channels are connected in series and include a differential input coupled to the non-resistive circuit element. One input of a differential input of a first measurement channel of the multiple measurement channels is connected to the first terminal of the electronic circuit and one input of a differential input of a second measurement channel of the multiple measurement channels is connected to the second terminal of the electronic circuit. The combining circuit receives multiple outputs from the multiple measurement channels and produce a composite output signal.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Inventors: Joseph L. Sousa, Micah Galletta O'Halloran, Andrew Joseph Thomas
  • Patent number: 8018370
    Abstract: A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: September 13, 2011
    Assignee: Linear Technology Corporation
    Inventors: Andrew J. Thomas, Joseph L. Sousa
  • Publication number: 20110187573
    Abstract: A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 4, 2011
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventors: Andrew J. Thomas, Joseph L. Sousa
  • Patent number: 7907074
    Abstract: Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: March 15, 2011
    Assignee: Linear Technology Corporation
    Inventors: Alfio Zanchi, David M. Thomas, Joseph L. Sousa, Andrew J. Thomas, Jesper Steensgaard-Madsen
  • Patent number: 7683695
    Abstract: Systems and methods for reducing the magnitude of signal dependent capacitance are provided. Capacitance canceling circuitry is operative to generate cancellation capacitance in response to the magnitude of a signal, which may be the same signal that produces the undesired signal dependent capacitance, to at least partially cancel the signal dependent capacitance.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 23, 2010
    Assignee: Linear Technology Corporation
    Inventors: Joseph L. Sousa, David M. Thomas
  • Publication number: 20090121912
    Abstract: Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant.
    Type: Application
    Filed: October 9, 2008
    Publication date: May 14, 2009
    Inventors: Alfio Zanchi, David M. Thomas, Joseph L. Sousa, Andrew J. Thomas, Jesper Steensgaard-Madsen
  • Patent number: 6522187
    Abstract: A CMOS switch with compensation circuitry that maintains linearized gate capacitance, said switch capable of selectively processing a signal independent of changes to gate capacitance current. The switch passes signals which are substantially insensitive to changes in source impedance. Thus, the switch processes an analog signal with a minimum of distortion as a result of gate capacitance currents.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: February 18, 2003
    Assignee: Linear Technology Corporation
    Inventor: Joseph L. Sousa
  • Patent number: 5831562
    Abstract: A full differential sample and hold circuit for an analog to digital converter. The sample and hold circuit samples and holds the differential signal resulting from two input signals. The sample and hold circuit includes a comparator, two differential capacitors and a common mode sample and hold circuit. The comparator has two input terminals and an output terminal. Each of the differential capacitors corresponds to one of the input signals and has an input terminal adapted for selective coupling to the respective input signal. Each of the differential capacitors has an output terminal electrically coupled to a different input terminal of the comparator. The common mode sample and hold circuit is disposed between the input terminals of the two differential capacitors. In one embodiment, the common mode sample and hold circuit comprises two common mode capacitors.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: November 3, 1998
    Assignee: Sipex Corporation
    Inventors: Jeffrey B. Van Auken, Joseph L. Sousa
  • Patent number: 5638072
    Abstract: A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: June 10, 1997
    Assignee: Sipex Corporation
    Inventors: Jeffrey B. Van Auken, Joseph L. Sousa