Abstract: A vertically integrated circuit assembly may include a substrate including a plurality of electrical traces, and a first circuit assembly layer disposed on the substrate. In embodiments, the first circuit assembly layer includes a first set of integrated circuit components, and a plurality of electrical interconnects configured to route signals through the first circuit assembly layer. In embodiments, the vertically integrated circuit assembly further includes a second circuit assembly layer coupled to the top surface of the first circuit assembly layer. The second circuit assembly layer may include a second set of integrated circuit components, and a plurality of electrical interconnects configured to route signals through the second circuit assembly layer. In embodiments, an electrical interconnect arrangement on a top surface of the first circuit assembly layer is configured to interface with an electrical interconnect arrangement on the bottom surface of the second circuit assembly layer.

Abstract: Electronically scanned array (ESA) antennas are disclosed. An antenna may include an electronically scanned array (ESA) panel. The ESA panel may include a plurality of transmit/receive (T/R) modules, and each T/R module of the plurality of T/R modules may be contained within a unit cell of the ESA panel, where the unit cell has a surface area constrained by a maximum operating frequency of the ESA panel. The antenna may also include at least one radio frequency (RF) filter positioned within each particular unit cell of the ESA panel. The at least one RF filter may be configured to provide RF filtering specifically for the T/R module co-located within that particular unit cell of the ESA panel.

Abstract: Electronically scanned array (ESA) antennas are disclosed. An antenna may include an electronically scanned array (ESA) panel. The ESA panel may include a plurality of transmit/receive (T/R) modules, and each T/R module of the plurality of T/R modules may be contained within a unit cell of the ESA panel, where the unit cell has a surface area constrained by a maximum operating frequency of the ESA panel. The antenna may also include at least one radio frequency (RF) filter positioned within each particular unit cell of the ESA panel. The at least one RF filter may be configured to provide RF filtering specifically for the T/R module co-located within that particular unit cell of the ESA panel.

Abstract: The present invention is a Chip Scale Atomic Clock (CSAC)-enabled Time and Frequency Standard (CTFS) architecture. The CTFS architecture includes a microcontroller, a Time Compensated Crystal Oscillator (TCCO) circuit which is connected to the microcontroller, and a Chip Scale Atomic Clock (CSAC) which is connected to the microcontroller. The microcontroller is configured for selectively causing the CTFS to provide a TCCO circuit-based output frequency when the CTFS has not locked to a predetermined atomic resonance, and is further configured for causing the CTFS to provide a CSAC-based output frequency when the CTFS has locked to a predetermined atomic resonance.