Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.

Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive.

Abstract: The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.

Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Abstract: The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.

Abstract: The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.

Abstract: Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.

Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log.

Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive.

Abstract: The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. The write look ahead information can include information about the location where data would have next been written to a memory system.

Abstract: The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log.