Abstract: A cache memory system in a computing system has a first cache module storing data, a second cache module storing data, and a controller writing data simultaneously to both the first and second cache modules. A second controller can be added to also write data simultaneously to both the first and second cache modules. In a single write cycle each controller requests access to both the first and second cache modules. Both cache modules send an acknowledgement of the cache request back to the controllers. Each controller in response to the acknowledgements from both of the cache modules simultaneously sends the same data to both cache modules. Both of the cache modules write the same data into cache in their respective cache modules.

Abstract: A distributor apparatus and its method of operation for interconnecting a node of a bus in a node-limited serial data bus computer network to a plurality of subnode devices. A transmission on the bus is distributed or routed through the distributor to each subnode device connected thereto. A transmission from a subnode device is coupled to the bus through the distributor after the distributor selects one transmitting subnode device in the event that there are more than one subnode devices transmitting or requesting to transmit. Selection of one transmitting subnode device is carried out by rotating priority arbitration that occurs during an idle timing interval or quiet slot such that bus timing parameters are obeyed.