Patents by Inventor Joseph M. Moran

Joseph M. Moran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112574
    Abstract: A parking enforcement device can be secured to a surface adjacent to the area designated as NO PARKING. The enforcement device can include an elongated hollow body, a window provided to the tubular body, a battery, an internal frame assembly disposed inside of the elongated hollow body, and a camera disposed inside of the elongated hollow body. The internal frame assembly defines a cavity in which the battery is located. A camera support pole extends vertically upwards from the internal frame assembly. The camera is secured to the camera support pole and located vertically along the camera support pole such that the camera views outward through the window. A solar panel can be provided atop the parking enforcement device to recharge the battery.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 4, 2024
    Inventors: Mark J. MORAN, James MARTIN, James CONLAN, Richard W. KELLEY, II, Steven B. LANE, Alexander J. PALUMBO, Marcus N. SCHMIDT, Joseph M. CALDWELL
  • Patent number: 6764228
    Abstract: A hermetic package having connectors, such as optical fibers or electrical leads, connected and bonded thereto with a bonding material such as epoxy resin, has the bonding material coated with a single layer or multiple layers of sealing material, such as chromium, copper, gold, tungsten, titanium, nickel, or aluminum, to prevent outgased material from the bonding material from entering the hermetic package enclosure. The bonding material may be recessed prior to coating of the sealing material to permit the sealing material to be polished from the optical element and the optical element polished flush with the inside of the package while leaving the sealing material covering the bonding material.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: July 20, 2004
    Assignee: Veritech, Inc.
    Inventor: Joseph M. Moran
  • Patent number: 6690875
    Abstract: Alignment of an array of N elements, such as optical fibers, within a preselected tolerance value is obtained using a primary substrate with a plurality of N apertures extending therethrough from a first surface to a second opposing surface. Each aperture, at its narrowest point, has a cross-section that is greater than a cross-section of an element to be inserted therethrough. Each of the elements passes through its corresponding aperture and rests against the same corresponding point and/or sidewall of the aperture so as to result in the desired alignment. A directing arrangement directs the elements toward the primary substrate at a predetermined angle to cause a spring-like action to occur in each of the elements when threaded through its associated aperture for aligning the elements to engage the same corresponding point and/or sidewall of the aperture.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: February 10, 2004
    Assignee: Veritech, Inc.
    Inventor: Joseph M. Moran
  • Publication number: 20030147603
    Abstract: A hermetic package having connectors, such as optical fibers or electrical leads, connected and bonded thereto with a bonding material such as epoxy resin, has the bonding material coated with a single layer or multiple layers of sealing material, such as chromium, copper, gold, tungsten, titanium, nickel, or aluminum, to prevent outgased material from the bonding material from entering the hermetic package enclosure. The bonding material may be recessed prior to coating of the sealing material to permit the sealing material to be polished from the optical element and the optical element polished flush with the inside of the package while leaving the sealing material covering the bonding material.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 7, 2003
    Inventor: Joseph M. Moran
  • Publication number: 20030123835
    Abstract: Alignment of an array of N elements, such as optical fibers, within a preselected tolerance value is obtained using a primary substrate with a plurality of N apertures extending therethrough from a first surface to a second opposing surface. Each aperture, at its narrowest point, has a cross-section that is greater than a cross-section of an element to be inserted therethrough. Each of the elements passes through its corresponding aperture and rests against the same corresponding point and/or sidewall of the aperture so as to result in the desired alignment. A directing arrangement directs the elements toward the primary substrate at a predetermined angle to cause a spring-like action to occur in each of the elements when threaded through its associated aperture for aligning the elements to engage the same corresponding point and/or sidewall of the aperture.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventor: Joseph M. Moran
  • Patent number: 6522817
    Abstract: Preselected alignment of an array of N optical fibers is obtained using a relatively thick primary substrate with a thin layer mounted thereon. The primary substrate has a sufficient structure to support an array of N spaced-apart optical fibers passing therethrough. The primary substrate has first and second opposing surfaces and defines a plurality of N primary substrate apertures which each extend therethrough from the first surface to the second surface and have a cross-section which is greater than a cross-section of an optical fiber such that one of the N optical fibers can be inserted through each of the N primary substrate apertures. The layer is metal, is relatively thin, and engages one of the first and second opposing surfaces of the primary substrate, and defines N layer apertures therethrough. Centers of the layer apertures are aligned to a preselected tolerance value which is required for the array of elements.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: February 18, 2003
    Assignee: Veritech, Inc.
    Inventor: Joseph M. Moran
  • Publication number: 20020154882
    Abstract: Preselected alignment of an array of N optical fibers is obtained using a relatively thick primary substrate with a thin layer mounted thereon. The primary substrate has a sufficient structure to support an array of N spaced-apart optical fibers passing therethrough. The primary substrate has first and second opposing surfaces and defines a plurality of N primary substrate apertures which each extend therethrough from the first surface to the second surface and have a cross-section which is greater than a cross-section of an optical fiber such that one of the N optical fibers can be inserted through each of the N primary substrate apertures. The layer is metal, is relatively thin, and engages one of the first and second opposing surfaces of the primary substrate, and defines N layer apertures therethrough. Centers of the layer apertures are aligned to a preselected tolerance value which is required for the array of elements.
    Type: Application
    Filed: December 18, 2000
    Publication date: October 24, 2002
    Inventor: Joseph M. Moran
  • Patent number: 5023557
    Abstract: Electronic devices such as hybrid integrated circuits such as those having test points spaced less than 1250 .mu.m are advantageously evaluated utilizing a two-probe process. In this process the probes are moved between test points in a pattern that reduces movement distance without concern for any ordering imposed by the nets themselves or the test to be made. Additionally, the test is made so that the movement time is the limiting factor.
    Type: Grant
    Filed: September 5, 1990
    Date of Patent: June 11, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Joseph M. Moran, Thomas C. Russell
  • Patent number: 4901013
    Abstract: An apparatus for testing of electrical circuits has a buckling beam probe assembly having advantageous features that make it useful for contacting area arrays of test points, and for reliably establishing contact therewith. The probe elements remain essentially parallel even in the buckled state, and the probe tips execute a small "wiping" movement on the contact point. In some preferred embodiments the probe tips are shaped to result in reduced contact area.
    Type: Grant
    Filed: August 19, 1988
    Date of Patent: February 13, 1990
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: William E. Benedetto, Joseph M. Moran
  • Patent number: 4683024
    Abstract: A new method for fabricating a device, such as a semiconductor device, is disclosed. The method includes the step of patterning a substrate with a trilevel resist containing a spin-deposited substitute for the conventional central, silicon dioxide region. This substitute includes an organosilicon glass resin in combination with metal-and-oxygen containing material. The inventive method prevents the losses of linewidth control, and avoids the pattern degradation due to undesirably many pinholes, of previous such methods.
    Type: Grant
    Filed: February 4, 1985
    Date of Patent: July 28, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: David A. Miller, Joseph M. Moran, Gary N. Taylor
  • Patent number: 4680084
    Abstract: The invention involves new etch monitoring and thickness measurement techniques which are more accurate than previous techniques. In accordance with the invention, the etch depth of a substrate region undergoing etching is monitored, or the thickness of the region is measured, by impinging the region with light and detecting the intensity of the reflected light. In contrast to the previous techniques, the incident light is chosen so that a substrate region underlying, and/or a patterned substrate region overlying the substrate region of interest is substantially opaque to the incident light, which precludes the formation of signals unrelated to etch depth or thickness.
    Type: Grant
    Filed: August 21, 1984
    Date of Patent: July 14, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Peter A. Heimann, Joseph M. Moran, Ronald J. Schutz
  • Patent number: 4400235
    Abstract: In a plasma-assisted dry etching process designed to pattern VLSI devices, a relatively high and uniform etch rate exhibiting low contamination is achieved over the entire surface extent of each wafer to be etched. This is accomplished by mounting the wafers in a unique fashion on one of two spaced-apart electrodes in the reaction chamber of a dry etching system. In particular, the front surface of each wafer is maintained in substantially the same plane as that of surrounding dielectric material. Additionally, the thickness of the surrounding dielectric material is designed to be considerably greater than the thickness of any dielectric material in contact with the back surface of each wafer. In that way, the entire front surface extent of each wafer is influenced by a relatively uniform electric field. Moreover, the available field in the chamber is in effect focussed onto the wafer surfaces, thereby achieving a relatively high etch rate characterized by low contamination.
    Type: Grant
    Filed: March 25, 1982
    Date of Patent: August 23, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Gerald A. Coquin, Joseph M. Moran, Gary N. Taylor
  • Patent number: 4397724
    Abstract: In a plasma-assisted etching apparatus and method, surfaces in the reaction chamber are covered with a layer of a polyarylate polymer. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.
    Type: Grant
    Filed: August 24, 1981
    Date of Patent: August 9, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Joseph M. Moran
  • Patent number: 4333793
    Abstract: In a VLSI device fabrication process, erosion of a patterned resist layer (16, 18) during dry etching of an underlying layer (14) can significantly limit the high-resolution patterning capabilities of the process. As described herein, a protective polymer layer (60, 62) is formed and maintained only on the resist material (16, 18) while the underlying layer (14) is being etched. High etch selectivities are thereby achieved. As a consequence, very thin resist layers can be utilized in the fabrication process and very-high-resolution patterning for VLSI devices is thereby made feasible.
    Type: Grant
    Filed: October 20, 1980
    Date of Patent: June 8, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Nadia Lifshitz, Joseph M. Moran, David N. Wang
  • Patent number: 4244799
    Abstract: In an integrated circuit fabrication sequence, a relatively thick sacrificial layer (18) is deposited on a nonplanar surface of a device wafer in which high-resolution features are to be defined. The thick layer is characterized by a conforming lower surface and an essentially planar top surface and by the capability of being patterned in a high-resolution way. An intermediate masking layer (22) and then a thin resist layer (20) are deposited on the top surface of the sacrificial layer, the thickness of the resist layer being insufficient by itself to provide adequate step coverage if the resist layer were applied directly on the nonplanar surface. A high-resolution pattern defined in the resist layer is transferred into the intermediate masking layer. Subsequently, a dry processing technique is utilized to replicate the pattern in the sacrificial layer. A high-resolution pattern with near-vertical sidewalls is thereby produced in the sacrificial layer.
    Type: Grant
    Filed: September 11, 1978
    Date of Patent: January 13, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: David B. Fraser, Dan Maydan, Joseph M. Moran
  • Patent number: 4225664
    Abstract: A mixture of poly(2,3-dichloro-1-propyl acrylate) and poly(glycidyl methacrylate-co-ethyl acrylate), with the latter forming between 1 percent and 20 percent by weight, of the total polymer mixture, has been found to form an x-ray resist having adhesive and resolving properties superior to those of poly(2,3-dichloro-1-propyl acrylate) which is a good x-ray resist material. Superior properties of the mixture are attributed to the fact that the two polymers form a compatible polymer mixture which is a relatively rare and unpredictable event in polymer chemistry.
    Type: Grant
    Filed: February 22, 1979
    Date of Patent: September 30, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Joseph M. Moran, Gary N. Taylor
  • Patent number: 4185202
    Abstract: X-ray lithographic systems as heretofore constructed include a low-attenuation chamber for propagating x-rays from a source toward a mask member that is positioned in close proximity to a resist-coated wafer. Both the mask and the wafer are included in the chamber which typically is either filled with helium or evacuated to a pressure less than about 10.sup.-2 Torr. In accordance with this invention, an x-ray lithographic system is constructed to enable establishment in the wafer-to-mask region of a controlled atmosphere that is separate and distinct from that maintained in the low-attenuation chamber. In this way, an improved lithographic system with advantageous throughput and other characteristics is realized.
    Type: Grant
    Filed: December 5, 1977
    Date of Patent: January 22, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Robert E. Dean, Dan Maydan, Joseph M. Moran, Gary N. Taylor