Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure.

Abstract: Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node.

Abstract: Compensation circuit means for inclusion in an off-chip driver circuit is provided to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. The compensation circuit means, which is coupled across the output transistor circuit of the off-chip driver, may comprise one or more serially connected diodes. The diode (or diodes) may be formed by the base collector junction of a bipolar transistor.

Abstract: A driver circuit for a capacitively loaded line employs the charge storage capacitance of a diode for raising the base of a driver transistor above the circuit power supply voltage level so as to pull up the line to within a transistor base-emitter voltage drop of the power supply voltage level. The driver is easily fabricated in integrated circuit form, as no capacitors, either on or off chip, are required.The driver circuit includes a driver transistor, the collector of which is connected to the power supply and the emitter of which is connected to the line. A switching transistor has an input voltage applied between its base and emitter. A diode is connected between the switching and driver transistors, the anode being connected to the base of the driver transistor, and the cathode being connected to the collector of the switching transistor.

Abstract: A current controlled gate performing a NOR function utilizes a pair of transistors acting as current mirrors that receive a DC bias through a large resistor. This bias occurs when an input transistor is positive to insure that one of the current mirror transistors will saturate when the input transistors are "off" and the other will be driven into saturation when either of the input transistors is "on". When all inputs are negative, one of the current mirror transistors saturates thereby reducing the current to the input transistors effectively to zero. The saturation results in the collector-base capacitance increasing very rapidly such that the input assumes the characteristics of a common emitter due to the large capacitance existing in the collector of the current mirror transistor. An active push-pull output is produced with a single collector path from input to output.

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).