Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

Abstract: A switching regulator includes a low-side switching transistor, a snubber transistor, a first pull-down transistor, and a second pull-down transistor. The low-side switching transistor includes a first current terminal and a second current terminal. The first current terminal is coupled to a switching node. The second current terminal is coupled to a ground terminal. The snubber transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to the switching node. The second current terminal is coupled to the ground terminal. The first pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal. The second pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal.

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

Abstract: In the described examples, a driver includes a signal controller that provides a gate control signal to a gate buffer coupled to a gate of a transistor and a field plate control signal to a field plate buffer coupled to a field plate of the transistor. The signal controller provides a rising edge on the field plate control signal causing the field plate buffer to provide a bias voltage on the field plate of the transistor a predetermined amount of time after providing a rising edge on the gate control signal that causes the gate buffer to provide a turn-on voltage on the gate of the transistor that causes the transistor to transition from a cutoff region to a saturation region and to a linear region.

Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to adjust a transient response. An example apparatus includes a clamping circuit including a first input, a second input, a third input, and an output, wherein the first input is adapted to be coupled to a selector, a reference voltage generator including an output, wherein the output of the reference voltage generator is coupled to the second input of the clamping circuit, an error amplifying circuit including an output, wherein the output of the error amplifying circuit is coupled to the third input of the clamping circuit, and a pulse width modulator including an input, wherein the input of the pulse width modulator is coupled to the output of the clamping circuit.

Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to adjust a transient response. An example apparatus includes a clamping circuit including a first input, a second input, a third input, and an output, wherein the first input is adapted to be coupled to a selector, a reference voltage generator including an output, wherein the output of the reference voltage generator is coupled to the second input of the clamping circuit, an error amplifying circuit including an output, wherein the output of the error amplifying circuit is coupled to the third input of the clamping circuit, and a pulse width modulator including an input, wherein the input of the pulse width modulator is coupled to the output of the clamping circuit.

Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.

Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.

Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.

Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.

Abstract: Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.

Abstract: In the described examples, a driver includes a signal controller that provides a gate control signal to a gate buffer coupled to a gate of a transistor and a field plate control signal to a field plate buffer coupled to a field plate of the transistor. The signal controller provides a rising edge on the field plate control signal causing the field plate buffer to provide a bias voltage on the field plate of the transistor a predetermined amount of time after providing a rising edge on the gate control signal that causes the gate buffer to provide a turn-on voltage on the gate of the transistor that causes the transistor to transition from a cutoff region to a saturation region and to a linear region.

Abstract: A method includes determining that a current at an inductor in a series transfer capacitor buck converter is decaying to zero during a first cycle. The method also includes, in response to determining that the current at the inductor is decaying to zero, enabling an electrostatic discharge (ESD) structure and turning off a low side transistor. The ESD structure is disposed at a node connecting the low side transistor, a high side transistor and the inductor. The method further includes disabling the ESD structure before the high side transistor is turned on during a next cycle following the first cycle.

Abstract: A power converter includes at least a first phase including a high-side MOSFET transistor (HSA) and a low-side (LS) MOSFET transistor (LSA) driving a first output inductor. The first phase further includes an active gate drive assist circuit including first MOSFET switch (first switch) and second MOSFET switch (second switch) positioned in series between a source of HSA and a drain of LSA. A capacitor (CS) is between the source of HSA and drain of LSA. A bootstrap capacitor (CA) having a reference terminal is connected to a node between the first switch and the second switch.

Abstract: A multiphase DC-to-DC synchronous power converter, which has a number of converter channels that generate a corresponding number of current sense signals, blanks the current sense signals in a first converter channel for periods of time that correspond with the actions of the transistors in a second converter channel, where the actions result in noise spikes across the converter that falsely interfere with current sensing in the first converter channel.

Abstract: A multiphase DC-to-DC synchronous power converter, which has a number of converter channels that generate a corresponding number of current sense signals, blanks the current sense signals in a first converter channel for periods of time that correspond with the actions of the transistors in a second converter channel, where the actions result in noise spikes across the converter that falsely interfere with current sensing in the first converter channel.

Abstract: A multiphase DC-to-DC synchronous power converter, which has a number of converter channels that generate a corresponding number of current sense signals, blanks the current sense signals in a first converter channel for periods of time that correspond with the actions of the transistors in a second converter channel, where the actions result in noise spikes across the converter that falsely interfere with current sensing in the first converter channel.

Abstract: A power circuit combination includes a series capacitor buck converter including a first half-bridge including a first high side power switch (HSA), first low side power switch (LSA) and a second half-bridge. A transfer capacitor (Ct) is connected in series with HSA and LSA, and between the first and second half-bridges. An adaptive HS driver circuit has an output coupled to a gate of HSA and includes a power supply circuit including a summing circuitry that dynamically outputs a variable power supply level (VGX) based on a fixed voltage and a voltage across Ct, a buffer driver, and a boost capacitor (CA) across the buffer driver. VGX is coupled to a positive terminal of CA. The power supply circuit is configured so that as a voltage across Ct varies, VGX adjusts so that a voltage across CA is changed less than a change in voltage across Ct.