Abstract: In an example, a system comprises a boost power factor correction (PFC) converter that includes a thermistor, an inductor, and a transistor and a PFC controller coupled to a common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a terminal of the transistor. A first flip-flop is coupled to the comparator and to a control terminal of the transistor. A zero current detector is coupled to the inductor. A timer is coupled to the comparator and to the zero current detector. A second flip-flop is coupled to the timer and to the control terminal of the transistor. An AND gate is coupled to the first and second flip-flops. The circuit includes third and fourth flip flops.

Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

Abstract: Example embodiments of the systems and methods of CCM primary-side regulation disclosed herein subtract an estimate of the secondary IR drop from each output voltage sample. This allows a fixed sample instant to be set (with regard to the beginning of the off or flyback interval), and removes the need to hunt for or adjust to an optimum sample instant, or one with minimum IR drop error. The estimate of the IR drop may be adjusted on a cycle-by-cycle basis, based on the commanded primary peak current, knowing that the peak secondary current will be directly proportional by the turns ratio of the transformer. For improved accuracy, an adjustment may be made for the decay of secondary current during the delay to the sample instant, if the inductance value is known.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: A Power Factor Correction (PFC) controller includes an error amplifier for amplifying a difference between Vout and intended Vout to provide a power demand (Pdem) output at a compensation pin. A burst mode controller includes soft-start circuitry coupled to receive Pdem and to a drive pin which provides pulses to a control node of a power switch of a DC-DC converter during burst periods. The pulses slow ramping of line current over a first 2 to 36 switching cycles at a beginning of bursts when energizing the inductor to reduce a line current slope as compared to without ramping up, and for slowing ramping down of line current over the last 2 to 36 switching cycles to reduce a line current slope when de-energizing the inductor as compared to a line current without ramping down. The PFC controller does not utilize zero-crossings of the line voltage for burst period synchronization.

Abstract: A Power Factor Correction (PFC) controller includes an error amplifier for amplifying a difference between Vout and intended Vout to provide a power demand (Pdem) output at a compensation pin. A burst mode controller includes soft-start circuitry coupled to receive Pdem and to a drive pin which provides pulses to a control node of a power switch of a DC-DC converter during burst periods. The pulses slow ramping of line current over a first 2 to 36 switching cycles at a beginning of bursts when energizing the inductor to reduce a line current slope as compared to without ramping up, and for slowing ramping down of line current over the last 2 to 36 switching cycles to reduce a line current slope when de-energizing the inductor as compared to a line current without ramping down. The PFC controller does not utilize zero-crossings of the line voltage for burst period synchronization.

Abstract: At least some aspects of the present disclosure provide for a circuit. In one example, the circuit includes a logic circuit having multiple inputs and multiple outputs, a calculated discontinuous conduction (DCM) (TDCM) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, an on-time (TON) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, and a hysteresis timer having an input coupled to one of the logic circuit outputs and multiple outputs coupled to multiple of the logic circuit inputs.

Abstract: Disclosed examples include methods and control circuits to operate a single or multi-phase DC-DC converter, including an output that turns a first switch on for a controlled on time and then turns the switch off for a controlled off time in successive control cycles, as well as a PWM circuit that computes a threshold time value corresponding to a predetermined peak inductor current and a duty cycle value, and computes a first time value according to an error value for a subsequent second switching control cycle. The PWM circuit sets the on time to the first time value to operate in a critical conduction mode for the second switching control cycle when the first time value is greater than or equal to the threshold time value, and otherwise sets the controlled on time to the threshold time value for discontinuous conduction mode operation in the second control cycle.

Abstract: An LLC converter includes an input having a first node and a second node. A first switch is coupled between the first node and a third node and a second switch is coupled between the third node and the second node. A transformer having a first transformer input is coupled to the third node. A resonant capacitor is coupled to a second transformer input and a first input of a summer. A voltage ramp generator is coupled to a second input of the summer, the summer for summing voltages at the first input and the second input. The converter further includes circuitry for generating control signals for the first switch and the second switch in response to the output of the summer.

Abstract: A power factor correction (PFC) pre-converter includes a boost converter and a PFC controller. The boost converter is configured to step up a boost converter input voltage by generating a boost converter output voltage. The boost converter includes an inductor, a switch, and a diode. The PFC controller is configured to control the switch by generating a signal causing the switch to be closed for a first period of time. The first period of time ends when current through the inductor reaches a target current value. The PFC controller is also configured to control the switch by, in response to the first period of time ending, generating a signal causing the switch to be open for a second period of time. The second period of time is based on a ratio between the first period of time and a critical conduction mode on time.

Abstract: An LLC converter includes an input having a first node and a second node. A first switch is coupled between the first node and a third node and a second switch is coupled between the third node and the second node. A transformer having a first transformer input is coupled to the third node. A resonant capacitor is coupled to a second transformer input and a first input of a summer. A voltage ramp generator is coupled to a second input of the summer, the summer for summing voltages at the first input and the second input. The converter further includes circuitry for generating control signals for the first switch and the second switch in response to the output of the summer.

Abstract: Example embodiments of the systems and methods of CCM primary-side regulation disclosed herein subtract an estimate of the secondary IR drop from each output voltage sample. This allows a fixed sample instant to be set (with regard to the beginning of the off or flyback interval), and removes the need to hunt for or adjust to an optimum sample instant, or one with minimum IR drop error. The estimate of the IR drop may be adjusted on a cycle-by-cycle basis, based on the commanded primary peak current, knowing that the peak secondary current will be directly proportional by the turns ratio of the transformer. For improved accuracy, an adjustment may be made for the decay of secondary current during the delay to the sample instant, if the inductance value is known.