Abstract: A circuit for the analog correlation of a signal to remove impairments such as echo, cross talk and intersymbol interference is described. A duplexing circuit which improves echo response by providing a second transformer is described.

Abstract: A method and an apparatus for slicing an analog signal using an analog encoder.

Abstract: A method and apparatus for joint training of an analog equalizer (AEQ) and an analog echo canceller (AEC) is described. In one embodiment, which both the AEQ and AEC process an input analog signal in the analog domain. In one embodiment, the method includes joint training the AEQ and the AEC using independent analog error signals.

Abstract: A method and an apparatus for slicing a multilevel analog signal using a two-level slicer having one threshold level to generate an analog error signal. The method may be performed by delaying a received multilevel analog signal in a plurality of serial analog stages (n), further delaying a multilevel analog signal tapped from stage n, combining the further delayed signal from stage n with an analog error signal e(t) to provide an analog weighting function Wn, wherein the combining of the delayed signal from stage n with Wn results in a plurality of signals XnWn, summing the plurality of signals XnWn, slicing a multilevel analog signal resulting from the summing of the plurality of signals XnWn using one threshold level to generate the analog error signal e(t), and combining the delayed signal from stage n with Wn.

Abstract: A circuit for the analog correlation of a signal to remove impairments such as echo, cross talk and intersymbol interference is described. A duplexing circuit which improves echo response by providing a second transformer is described.

Abstract: A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.

Abstract: A method and apparatus for joint training of an analog equalizer (AEQ) and an analog echo canceller (AEC), which both process an input analog signal in the analog domain. In one embodiment, the method includes joint training the AEQ and the AEC using independent analog error signals.

Abstract: A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.

Abstract: A low cost and low power adaptive cable equalizer that is particularly suitable for fast Ethernet data communication is disclosed. According to various embodiments of the present invention, first and second order adaptive equalizers are implemented using CMOS continuous-time analog signal processing, with variable resistors, linear capacitors and high-speed operational amplifiers.

Abstract: A digitally controlled tuner circuit for continuous-time filters. Active RC integrators include digitally programmable feedback capacitors to allow for digital fine tuning of their time constant. The PLL-based tuner circuit includes a sine-wave oscillator made up of the digitally-controlled active RC integrators.

Abstract: A high-speed low-voltage line-driver circuit implemented using various embodiments of high speed current-feedback opamps is disclosed. The line driver of the present invention uses a fully differential architecture whereby common-mode disturbances, such as noise due to substrate or power supply, are cancelled. The driver also uses a current-feedback approach to achieve larger bandwidth. In a specific embodiment, the current-feedback opamp used in the line driver of the present invention uses class A/B structure for both input and output stages.

Abstract: Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.

Abstract: Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.

Abstract: The output stage of a differential operational amplifier includes a source follower amplifier and a common source amplifier which are driven by two complementary outputs of a differential input stage. Continuous-time feedback circuits are provided to set the quiescent biasing conditions accurately. The differential operational amplifier has a low output impedance and a large output voltage swing with negligible open loop gain degradation when the size of the load resistance is varied. Floating compensation capacitors reduce the total capacitor value and the physical area needed for the operational amplifier.

Abstract: A CMOS operational amplifier comprises an output gain stage including output transistors coupled between the rails so that for a given amount of current, the output transistors have rail-to-rail gate-to-source voltages. The output transistors can be made smaller in size with the output stage being capable of driving a small resistive load with minimal signal distortion.

Abstract: An exponential analog-to-digital converter comprises two gain stages, each of which includes a binary-weighted capacitor array. The capacitors are switched in succession to multiply the gain of a sampled analog input signal, while a counter counts down for each switching step from an initial setting of binary 111. When the gain signal has a value outside a predetermined reference voltage range, a 3-bit binary digital word representative of the analog input signal sample is registered in the counter. If the gain signal produced after all the capacitors have been switched in to provide the maximum gain does not fall outside the reference range, then the binary word stored in the counter for the sample of the analog signal is 000.

Abstract: A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.