Patents by Inventor Joseph O. Marsh
Joseph O. Marsh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7659740Abstract: Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal.Type: GrantFiled: August 11, 2008Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
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Patent number: 7560966Abstract: A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at least one clock signal and having a mode control device for operating the CML latch circuit as a buffer amplifier when the at least one clock signal is inactive. The method comprises the steps of activating the mode control devices of each of the CML latches to operate each of the CML latches as a buffer; inputting a first signal to a first CML latch of the series; latching an output signal of a second CML latch of the series, the second CML latch being connected at a point in the series downstream from the first CML latch; and determining whether the output signal changes in accordance with a change in the first signal.Type: GrantFiled: December 19, 2007Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Joseph Natonio, James M. Wilson
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Publication number: 20090027075Abstract: A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.Type: ApplicationFiled: August 11, 2008Publication date: January 29, 2009Applicant: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
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Patent number: 7466156Abstract: A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.Type: GrantFiled: March 25, 2004Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
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Publication number: 20080129329Abstract: A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at least one clock signal and having a mode control device for operating the CML latch circuit as a buffer amplifier when the at least one clock signal is inactive. The method comprises the steps of activating the mode control devices of each of the CML latches to operate each of the CML latches as a buffer; inputting a first signal to a first CML latch of the series; latching an output signal of a second CML latch of the series, the second CML latch being connected at a point in the series downstream from the first CML latch; and determining whether the output signal changes in accordance with a change in the first signal.Type: ApplicationFiled: December 19, 2007Publication date: June 5, 2008Inventors: Joseph O. Marsh, Joseph Natonio, James M. Wilson
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Patent number: 7358787Abstract: A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.Type: GrantFiled: February 28, 2006Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Joseph Natonio, James M. Wilson
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Patent number: 7265696Abstract: In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.Type: GrantFiled: November 10, 2005Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, Joseph O. Marsh, Steven J. Zier
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Patent number: 7191305Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.Type: GrantFiled: September 28, 2004Date of Patent: March 13, 2007Assignee: International Business Machines CorporationInventors: William D. Corti, Joseph O. Marsh, Michael Won
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Patent number: 6834334Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.Type: GrantFiled: August 28, 2001Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: William D. Corti, Joseph O. Marsh, Michael Won
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Patent number: 6834360Abstract: An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.Type: GrantFiled: November 16, 2001Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: William D. Corti, Robert Kenny, Jr., Joseph O. Marsh, Steven C. Parker, Frank X. Scanzano, Michael Won
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Publication number: 20030097615Abstract: An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.Type: ApplicationFiled: November 16, 2001Publication date: May 22, 2003Applicant: International Business Machines CorporationInventors: William D. Corti, Robert Kenny, Joseph O. Marsh, Steven C. Parker, Frank X. Scanzano, Michael Won
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Publication number: 20030046509Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.Type: ApplicationFiled: August 28, 2001Publication date: March 6, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William D. Corti, Joseph O. Marsh, Michael Won
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Publication number: 20020195228Abstract: A thermal conductive tape article is provided which is adhered to the surface of an integrated circuit device to dissipate heat from the device. The thermal conductive tape article is preferably corrugated and may have a number of configurations providing an expanded surface area. The corrugated tape article may also have a metal strip bonded to one or both sides of the tape article to form a single-faced or double-faced corrugated tape article. The tape article is preferably made of copper or aluminum.Type: ApplicationFiled: June 7, 2001Publication date: December 26, 2002Applicant: International Business Machines CorporationInventors: William D. Corti, David C. Long, Joseph O. Marsh, Franics X. Scanzano, Michael Won, Tsorng-Dih Yuan