Abstract: A microprocessor chip which is capable of executing a specific subset of instructions on behalf of the main storage portion of a computer memory can be made to emulate direct execution instructions not in that specific subset while working on behalf a control storage portion of the computer memory in a manner which is transparent to the main storage portion by means of a novel set of operand space selection instructions in the control storage portion and a novel switching circuit on the microprocessor chip which controls the access of the chip to the control store portion and the main store portion.

Abstract: A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.

Abstract: Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.

Abstract: The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor, a secondary microprocessor, off-chip control storage belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage. The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines responsive to the particular microprocessor action being taken.

Abstract: A method for verifying the architectural integrity of a newly written or modified instruction set in a limited operating environment is described. More particularly, this methodology is adapted to perform such verification even though the processor under test has only a one or a few instructions in its partially complete instruction set. Such verification is accomplished using a minimum test driver, under control of a test processor, which loads the data necessary to execute the instruction being tested. The test system also provides actual or simulated I/O capabilities. After execution of that instruction, the test driver directs capture of the execution results for appropriate use. As an aid in performing the verification test, the test driver is provided with an invalid command that forces return of control to the test processor.

Abstract: Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. A mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.