Patents by Inventor Joseph P. Jarosz

Joseph P. Jarosz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9141743
    Abstract: Disclosed are methods, systems, and articles of manufactures for providing evolving information in generating a physical design with custom conductivity using force models and design space decomposition by first presenting a layout area in an interface. The interface then displays the evolution of the physical design in the interface to reflect temporal states of the physical design during generation of the physical design after the system receives an input for the physical design and a request for creating the physical design.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 22, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus C. McCracken, Joseph P. Jarosz
  • Patent number: 9135373
    Abstract: Disclosed are improved methods, systems, and computer program products for implementing an interface for visualizing, generating, and optimizing an I/O ring arrangement for an electronic design. A ribbon-based interface may be employed to visually see and control the design of the I/O ring.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 15, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joseph P. Jarosz, Thaddeus C. McCracken, Miles P. McGowan
  • Patent number: 9098667
    Abstract: Disclosed are methods, systems, and articles of manufactures for implementing a physical design with force directed placement or floorplanning and layout decomposition by identifying multiple nodes and then iteratively generating multiple cells by using the multiple nodes in a decomposition process and applying force model(s) to iteratively morph the cells until convergence criteria are satisfied to generate a layout or floorplan of an electronic design without requiring complete conductivity for the electronic design. The initially identified custom conductivity information is maintained throughout this iterative process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 4, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus C. McCracken, Joseph P. Jarosz
  • Patent number: 9092110
    Abstract: An approach is described for implementing a GUI that an account for illegal operations by the user. Visual ghosting is implemented that includes separation support. If an object is manipulated into an impermissible/unacceptable configuration, ghosting separation is performed to display multiple ghost images, where a first ghost image shows a legal configuration of the object and a second ghost image shows the current configuration of the object. The second ghost continues to track the user's manipulation of the object until a legal configuration is achieved. The improved approach provides a visual representation that corresponds to the expected end result, but is also be useful to track the user's actions if there is a violation.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: July 28, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Joseph P Jarosz
  • Patent number: 8677307
    Abstract: Disclosed are improved methods, systems, and computer program products for visualizing and estimating IC die arrangement for an electronic design, and for performing chip planning and estimation based upon the estimated and visualized IC die arrangements. According to some approaches, an interface is provided for visualizing different die arrangement options for an electronic design, in which a filmstrip view is provided to display smaller images of different die arrangement options, and a central viewing area is provided to view a larger image of a selected candidate die arrangement. The different images, whether smaller or larger images, are maintained with design object information and not just static images. This allows for selection and highlighting of individual objects within the die arrangement images, as well as corresponding highlighting of that same object in other images.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 18, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joseph P. Jarosz, Thaddeus C. McCracken
  • Patent number: 8375344
    Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: February 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Miles P. McGowan, Thaddeus Clay McCracken, Joseph P. Jarosz, Jeffrey Kim Ng
  • Publication number: 20100161303
    Abstract: An improved method, system, user interface, and computer program product is described for performing power-related inferences for an electronic design. According to some approaches, the electronic design is configured to include multiple power domains. Design information is used to infer the existence of power-management structures for and between the power domains in the electronic design. A graphical user interface is provided to visualize the inferred power-related structures and to allow the user to interact with and modify the design information related to power management.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Miles P. McGowan, Joseph P. Jarosz, Thaddeus Clay McCracken
  • Publication number: 20100153888
    Abstract: An approach is described for implementing a GUI that an account for illegal operations by the user. Visual ghosting is implemented that includes separation support. If an object is manipulated into an impermissible/unacceptable configuration, ghosting separation is performed to display multiple ghost images, where a first ghost image shows a legal configuration of the object and a second ghost image shows the current configuration of the object. The second ghost continues to track the user's manipulation of the object until a legal configuration is achieved. The improved approach provides a visual representation that corresponds to the expected end result, but is also be useful to track the user's actions if there is a violation.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Joseph P. Jarosz