Abstract: A method for determining motional branch current in an ultrasonic transducer of an ultrasonic surgical device over multiple frequencies of a transducer drive signal. The method may comprise, at each of a plurality of frequencies of the transducer drive signal, oversampling a current and voltage of the transducer drive signal, receiving, by a processor, the current and voltage samples, and determining, by the processor, the motional branch current based on the current and voltage samples, a static capacitance of the ultrasonic transducer and the frequency of the transducer drive signal.

Abstract: A back drill verification feature is provided on a layer of a circuit board. Before a back drill operation is performed, an electrical connection exists between conductive material in a via hole and the back drill verification feature. After the back drill operation, the electrical connection is severed.

Abstract: The use of operational configuration parameters to predict digital system failures is described herein. At least some illustrative embodiments include a method that includes initializing a digital system (the initializing comprising determining an operational configuration of at least part of the digital system), saving the operational configuration to a database stored on the digital system, reading the operational configuration from the database and comparing the operational configuration to a reference configuration, and identifying the digital system as being at risk of a future failure if at least one parameter of the operational configuration differs from the at least one same parameter of the reference configuration by more than a tolerance value.

Abstract: The use of operational configuration parameters to predict digital system failures is described herein. At least some illustrative embodiments include a method that includes initializing a digital system (the initializing comprising determining an operational configuration of at least part of the digital system), saving the operational configuration to a database stored on the digital system, reading the operational configuration from the database and comparing the operational configuration to a reference configuration, and identifying the digital system as being at risk of a future failure if at least one parameter of the operational configuration differs from the at least one same parameter of the reference configuration by more than a tolerance value.

Abstract: A method and apparatus of testing a computer having a controller includes adjusting a reference voltage signal from a first level to a second level in response to an output from the controller. The first level is a level of the reference voltage signal during normal operation of the computer. Operation of a receiver in the computer is tested with the reference voltage signal set at the second level. An input of the receiver is connected to the reference voltage signal. Next, the reference voltage signal is adjusted back from the second level to the first level to enable normal operation of the computer.

Abstract: A system comprises a bridge, a slot coupled to the bridge, and a power control unit coupled to the slot via a common power rail and coupled to the bridge. An add-in card having one of a plurality of types can be installed in the slot. Upon installing the add-in card, the bridge determines the type of add-in card and asserts a logic signal to the power control unit. Based on the logic signal, the power control unit provides one of a plurality of direct current (“DC”) voltages on the common power rail to the slot.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: A multi-pin edge connector assembly for connecting a daughter board to a mother board, for example, comprises a plurality of vias with conductive surfaces that are formed in the daughter board adjacent a connection edge. A plurality of openings are also formed in the daughter board, with each opening extending from the connection edge to one of the vias. Electrically conductive pins are positioned in the openings, with each pin having a first end in electrical contact with one of the conductive surfaces and a second end that projects beyond the connection edge for electrically contacting conductive pads or surfaces on the mother board. A retainer is mounted to the daughter board for holding the pins in their respective openings.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: Electrical signals are received corresponding to sets of digital data, and output optical signals are delivered, corresponding to the digital data, on at least two optical channels corresponding to different sets of the digital data, using light from a single light source. In another scheme, the optical switch may be integrated with an optical transmission medium (e.g., an optical cable).

Abstract: A device causing a faulty condition in a computer system having devices is isolated by detecting for a faulty condition associated with the devices and identifying the device causing the faulty condition. The devices are coupled to a bus. The faulty condition includes a bus hang condition. The devices are turned off when a bus hang condition is detected. The devices are then turned back on to test the devices. Each device is tested by writing and reading its configuration space. Information on the bus associated with the faulty condition is stored. The stored information is retrieved after the faulty condition has occurred, with the stored information including address, data, and bus control information.

Abstract: Data errors on a communications channel in a computer system are corrected. The data is transmitted over the communications channel in a sequence of time-multiplexed phases. A storage device accumulates the phases of data. An error detector and correction device checks the accumulated data for a data error and corrects the data error. The error detection and correction device can correct a one-bit data error, a two-bit data error, and a three-bit data error. Multiple bit errors can be corrected if the multiple bits of data are transmitted over one cable wire in multiple time phases. The communications channel carries the data over N sub-channels, and a parity check generator employs a predetermined parity check matrix based upon the N sub-channels and a probability that multiple errors in the accumulated data are attributable to a faulty sub-channel that affects the same data position in different time phases of the data.

Abstract: Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines.

Abstract: A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot of a computer system hot-pluggable, wherein a logic gate controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card whereas the other node is coupled to a bus to which the expansion slot is connected. The apparatus operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card from the bus when the system is running or during the powering up of the card.

Abstract: Control is switched from a first server to a second server in a fault tolerant system. The first and second servers are coupled with an expansion bus in an expansion box for communication with the expansion bus. An indication is provided to the second server to indicate the activity state of the first server. Communication between the first server and the expansion box is disabled if the indication indicates the first server is inactive. Communication between the second server and the expansion bus is disabled if the indication indicates that the first server is active. Communication between the second server is enabled if the indication indicates that the first server is inactive. The indication includes a heartbeat message transmitted periodically to the second server. The expansion bus includes a PCI bus.

Abstract: Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

Abstract: Electrical signals are received corresponding to sets of digital data, and output optical signals are delivered, corresponding to the digital data, on at least two optical channels corresponding to different sets of the digital data, using light from a single light source. In another scheme, the optical switch may be integrated with an optical transmission medium (e.g., an optical cable).

Abstract: Circuitry for tristating the address and data outputs of a processor to prevent a deadlock condition when the processor and another bus master is accessing a shared resource. The processor is located on a local bus and the other bus master is located on a PCI bus. Bi-directional tristate buffers are placed between the address and data output pins of the processor and the address and data portions of the first bus. If the processor is requesting a local-bus-to-PCI-bus cycle, and the PCI bus master is asserting a request for a local bus shared resource, the processor address and data output pins are tristated by the tristate buffers to allow the PCI bus master cycle to proceed. After the PCI bus master cycle completes, the tristate buffers are reenabled to allow the processor cycle to complete.