Abstract: A PMC (PCI Mezzanine Card) is disclosed which complies with the IEEE 1386 form factor specification and incorporates a PCMCIA card connector so that readily available PCMCIA cards can be used with a PMC. By removing approximately one-half of the usual PMC printed circuit board, space is created in which to mount the PCMCIA connector so that it is contained within the allowed component envelope above and below the surface of the PMC circuit board (4). The PCMCIA connector (10) is mounted by its leads to a tab (9) extending from circuit board (4). Side rails (15) having an s-shaped bend (18) extend from the circuit board (4) and provide mounting support for the bezel supports (2) thereby meeting the overall size requirements for PMC cards under the IEEE 1386 standard. The design of this invention also permits securing PCMCIA cards in the PCMCIA connector with set screws (21) that may be used to push in on extensions (13).

Abstract: There is provided a dynamic switch organization for error correction of a data path. The dynamic switch organization includes a data path for transmitting data information and control information and a crosspoint switch fabric having a plurality of inputs and a plurality of outputs along the data path. The crosspoint switch fabric has an arbitration bus and crosspoint switch boards coupled to the arbitration bus such that the boards are synchronized to process data in parallel. The crosspoint switch fabric also includes a control entity for directing data from one of the inputs to a particular one of the outputs, and the data includes data bits and check bits. The control entity is distributed among the crosspoint switch boards such that each board includes a portion of the control entity.

Abstract: There is provided a switching system that includes a plurality of input lines for transmitting time division multiplexed data signals, and a conversion means for receiving and converting the respective data signals into a non-time division multiplexed, parallel format, group of N data signals. The system also includes a crosspoint switch having a group of N/K outputs, a first group of N inputs connected to the respective outputs of the conversion means, and a second group of N/K select or control inputs. In addition, a control means includes connection memory that constitutes a means for addressing the crosspoint switch at the select inputs, and the outputs of a group of N/K multiplexers are connected to the select inputs and the inputs of the group of N/K multiplexers are connected to the control means.

Abstract: There is provided a fault tolerant clock system for a synchronous design using N-way combinatorial voting schemes for N greater than 3. The system comprises a plurality of clock circuits for generating clock signals and a voting circuit that is connected to each clock circuit for receiving the clock signals and generating an output signal. The voting circuit produces an output signal that is in agreement with a majority of the clock signals and maintains the output signal at a previous output level when the majority of the clock signals is not detected by the voting circuit. From another viewpoint, the voting circuit maintains the output signal at the previous current level when a minority of agreeing clock signals is not detected by the voting circuit.

Abstract: The apparatus detects a difference of frequency between a first signal having a first frequency and a second signal having a second frequency, the first and second signals being digital signals. A phase shifter shifts the first signal such that the first signal and the shifted first signal are sufficiently out of phase to keep the rising and falling edges of the two signals from occurring at the same time thereby avoiding subsequent simultaneous triggering conditions and jitter conditions between the first and second signal. A first gate samples the second signal by the shifted first signal to output a first sampled signal. A second gate samples the second signal by the first signal to output a second sampled signal. A sample gate samples the first sampled signal and the second sampled signal to generate a difference signal, the difference signal containing a difference value of the frequency difference between the first and second signal.