Abstract: A clock recovery circuit includes a resonant circuit which is driven into oscillation at a clock frequency by binary 1 pulses in a data signal supplied thereto, a clock signal being derived from the resonant circuit via a buffer and a limiting amplifier. The resonant circuit has a high Q to accommodate long sequences of binary Os during which it is not driven. In order to prevent over-driving when the data signal has a high density of binary 1s, a level detector detects when the oscillation amplitude exceeds a threshold level, whereupon a flip-flop is set to control a gate to inhibit driving of the resonant circuit until its oscillation amplitude has decayed. The flip-flop is clocked by the data signal to operate in synchronism with the incoming data, and may be followed by a second similarly clocked flip-flop to avoid potential errors.