Abstract: The present invention is an indirect analog synthesizer utilizing a direct analog fractional frequency multiplier approach. A fractional frequency multiplier produces a source that is injected into an offset loop of an indirect analog synthesizer. The fractional frequency multiplier utilizes a source and a combination of multipliers, dividers, and switches to generate and select among different frequencies. This direct analog approach eliminates step recovery diodes and sample loops from the frequency synthesizer. Switching speed of the direct analog portion is less than 100 nanoseconds. This increase in switching speed of the direct analog portion greatly improves the overall switching speed of the overall frequency synthesizer. Also, the fractional frequency multiplier has phase noise 20 dB better than a sampling loop. Better phase noise of the signal feeding the offset loop pushes optimum loop bandwidth of the offset loop higher, which also improves switching speed.

Abstract: A dual conversion, noise resistant, digitally-controlled mm-wave frequency synthesizer for generating rapidly-tunable RF signals. The prime signal-generation source is a 3.0-3.2 GHz low noise wide band voltage controlled oscillator (“vco”). The oscillator includes a buried stripline hairpin resonator having dual-tuning circuits to increase bandwidth coverage and unique bias circuitry to improve phase noise. The oscillator frequency is multiplied by a factor of two, yielding a 6.0-6.4 GHz signal that is mixed with a fixed locally generated carrier of 3900 MHz, the output of which represents the first Intermediate Frequency (IF). This IF is then mixed with 1950 MHz (3900 MHz divided by two), yielding a second IF that covers the 188 to 550 MHz range. The 2nd IF is divided down and phase locked to an external reference using a commercially available chip set. The 6.0-6.4 phase locked signal is then re-mixed with the 3.0-3.2 GHz output form the oscillator, thereby yielding a 9.0-9.6 GHz signal. The 9.