Patents by Inventor Joseph Perkalis

Joseph Perkalis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Column decoder configuration for a 1T/1C memory
    Patent number: 6856573
    Abstract: A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a fist bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: February 15, 2005
    Assignee: Ramtron International Corporation
    Inventors: Judith E. Allen, Dennis R. Wilson, Joseph Perkalis
  • Column decoder configuration for a 1T/1C memory
    Publication number: 20030210584
    Abstract: A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a fist bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
    Type: Application
    Filed: March 13, 2003
    Publication date: November 13, 2003
    Inventors: Judith E. Allen, Dennis R. Wilson, Joseph Perkalis