Abstract: A state machine in which the next state signals are biased by the next state encoder very close to the switch voltage of the input transistors of the present state latches to improve the response time of the state machine. Charge sharing on the outputs of the next state selector is prevented from affecting the biased next state signals by voltage substaining circuitry. By pre-encoding input signals pertinent to each state using separate input logic, the size of the next state selector is minimized, further improving the response time of the state machine. Selected present state latches may be prevented from changing state by gating the next state signals.

Abstract: A bi-directional bus isolation circuit couples the logic state present on a primary bus to a polysilicon secondary bus or the logic state present on the secondary bus to the primary bus in response to a select signal. A first NOR gate has one input coupled to the primary bus and a second input for receiving the select signal. A first output transistor couples the secondary bus to ground in response to the first NOR gate providing a logic high output. A second NOR gate has a first input coupled to the secondary bus, and a second input for receiving the select signal. A second output transistor couples the primary bus to ground in response to the second NOR gate providing a logic high output.

Abstract: A programmable edge defined output buffer clocks a first logic state to a first node when an input signal is in a first condition and a second logic state to a second node when the input signal is in a second condition. A programmable coupling circuit is programmable to couple the first and second nodes to an input of an amplifier. The programming selection determines in response to which signals will the first and second nodes be coupled to the input of the amplifier.

Abstract: A clocked buffer circuit is provided which uses a self-bootstrapping transistor to provide a full power supply output signal in response to an input signal and a full power supply clock signal. The self-bootstrapping transistor is disabled by a delay circuit prior to the removal of the clock signal so that the output signal is still provided after the removal of the clock signal. That the output signal reaches full power supply is ensured because the disabling effect of the delay circuit is triggered by the output signal itself.

Abstract: A three-state MOS circuit for buffering an input signal includes an edge definition circuit which is controlled by first and second independent clock signals. The edge definition circuit includes a first transistor for producing a low-to-high voltage transition when the input signal goes from a high to a low, and a second transistor for producing a high-to-low voltage transition in response to the input signal going from a low to a high. The generation of these high-to-low and low-to-high transitions are controlled by first and second independent clock signals. The output of the edge definition circuit is applied to a driver circuit which generates output control signals. The output control signals are applied to first and second output field effect transistors so as to generate a signal representative of the input signal.