Patents by Inventor Joseph R. Doucette

Joseph R. Doucette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9268393
    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth Sistla, Martin T. Rowland, Brian J. Griffith, Viktor D. Vogman, Joseph R. Doucette, Eric J. Dehaemer, Vivek Garg, Chris Poirier, Jeremy J. Shrall, Avinash N. Ananthakrishnan, Stephen H. Gunther
  • Patent number: 9141166
    Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng, Celeste M. Brown, Avinash N. Ananthakrishnan
  • Publication number: 20140157021
    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Inventors: Ankush Varma, Krishnakanth Sistla, Martin T. Rowland, Brian J. Griffith, Viktor D. Vogman, Joseph R. Doucette, Eric J. Dehaemer, Vivek Garg, Chris Poirier, Jeremy J. Shrall, Avinash N. Ananthakrishnan, Stephen H. Gunther
  • Publication number: 20120185706
    Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.
    Type: Application
    Filed: December 13, 2011
    Publication date: July 19, 2012
    Inventors: Krishnakanth V. Sistla, Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng, Celeste M. Brown, Avinash N. Ananthakrishnan