Patents by Inventor Joseph R. Zbiciak
Joseph R. Zbiciak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8707013Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.Type: GrantFiled: July 13, 2010Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Jagadeesh Sankaran, Joseph R. Zbiciak, Steven D. Krueger
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Patent number: 8683133Abstract: A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.Type: GrantFiled: January 20, 2009Date of Patent: March 25, 2014Assignee: Texas Instruments IncorporatedInventors: Sajish Sajayan, Alok Anand, Ashish Rai Shrivastava, Joseph R. Zbiciak
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Upgrade of low priority prefetch requests to high priority real requests in shared memory controller
Patent number: 8683134Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.Type: GrantFiled: January 20, 2009Date of Patent: March 25, 2014Assignee: Texas Instruments IncorporatedInventors: Sajish Sajayan, Alok Anand, Ashish Rai Shrivastava, Joseph R. Zbiciak -
Patent number: 8627032Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the permissions assigned to the request based on the memory segment being accessed. The decision to allow or disallow access is made by the extended memory controller by merging the permissions assigned to the memory segment being accessed, and the permissions assigned to the access request by the originating memory controller or other endpoint.Type: GrantFiled: August 5, 2011Date of Patent: January 7, 2014Assignee: Texas Instruments IncorporatedInventor: Joseph R. Zbiciak
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Patent number: 8301928Abstract: A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.Type: GrantFiled: January 20, 2009Date of Patent: October 30, 2012Assignee: Texas Instruments IncorporatedInventors: Sajish Sajayan, Alok Anand, Joseph R. Zbiciak
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Publication number: 20120272027Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the permissions assigned to the request based on the memory segment being accessed. The decision to allow or disallow access is made by the extended memory controller by merging the permissions assigned to the memory segment being accessed, and the permissions assigned to the access request by the originating memory controller or other endpoint.Type: ApplicationFiled: August 5, 2011Publication date: October 25, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Joseph R. Zbiciak
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Patent number: 8112652Abstract: This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. The hardware power down controller waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.Type: GrantFiled: January 20, 2009Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Sajish Sajayan, Alok Anand, Sudhakar Surendran, Ashish Rai Shrivastava, Joseph R. Zbiciak
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Publication number: 20120017067Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.Type: ApplicationFiled: July 13, 2010Publication date: January 19, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jagadeesh SANKARAN, Joseph R. ZBICIAK, Steven D. KRUEGER
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Patent number: 7890566Abstract: A functional unit in a digital system is provided with a rounding DOT product instruction, wherein a product of first pair of elements is combined with a product of second pair of elements, the combined product is rounded, and the final result is stored in a destination. Rounding is performed by adding a rounding value to form an intermediate result, and then shifting the intermediate result right. A combined result is rounded to a fixed length shorter than the combined product. The products are combined by either addition or subtraction. An overflow resulting from the combination or from rounding is not reported.Type: GrantFiled: October 31, 2000Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventor: Joseph R. Zbiciak
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Publication number: 20090249106Abstract: A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.Type: ApplicationFiled: January 20, 2009Publication date: October 1, 2009Inventors: Sajish Sajayan, Alok Anand, Joseph R. Zbiciak
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Publication number: 20090249105Abstract: This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.Type: ApplicationFiled: January 20, 2009Publication date: October 1, 2009Inventors: Sajish Sajayan, Alok Anand, Sudhakar Surendran, Ashish Rai Shrivastava, Joseph R. Zbiciak
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Upgrade of Low Priority Prefetch Requests to High Priority Real Requests in Shared Memory Controller
Publication number: 20090248992Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.Type: ApplicationFiled: January 20, 2009Publication date: October 1, 2009Inventors: Sajish Sajayan, Alok Anand, Ashish Rai Shrivastava, Joseph R. Zbiciak -
Publication number: 20090248991Abstract: A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.Type: ApplicationFiled: January 20, 2009Publication date: October 1, 2009Inventors: Sajish Sajayan, Alok Anand, Ashish Rai Shrivastava, Joseph R. Zbiciak
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Patent number: 7576758Abstract: Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at least one garland of closed chains of tiles. Each image includes a spanning set of these garlands. Rotation in place moves each pixel to the next location on its garland. On completion of a garland by return to the initial tile, tiles on the next garland are moved. Image rotation is complete after all the garlands have been traversed. This invention first linearized the two-dimensional tiles sliding into groups of super-pixels at contiguous locations above the image buffer. The tiles are rotated in place. The shuffled tiles are delinearized into rectangular blocks and then re-pitched if needed.Type: GrantFiled: March 8, 2006Date of Patent: August 18, 2009Assignee: Texas Instruments IncorporatedInventors: Sreenivas Kothandaraman, Joseph R. Zbiciak
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Patent number: 7546391Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.Type: GrantFiled: May 12, 2006Date of Patent: June 9, 2009Assignee: Texas Instruments IncorporatedInventors: Roger K. Castille, Natarajan Kurian Seshan, Marco Lazar, Joseph R. Zbiciak
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Patent number: 7315261Abstract: This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform tile from pixel form to bit plane form. This enables downstream algorithms to read only the data for the bit plane of interest. This greatly reduces the memory bandwidth bottleneck and opens many new optimization pathways.Type: GrantFiled: July 2, 2004Date of Patent: January 1, 2008Assignee: Texas Instruments IncorporatedInventor: Joseph R. Zbiciak
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Patent number: 6819684Abstract: A data communications subsystem (15) including a digital signal processor (DSP) (20) for performing bit insertion to preclude the inadvertent serial transmission of a protocol flag sequence is disclosed. A trigger sequence detection process (40) applies an infinite impulse response (IIR) filter to a current sequence of the input bitstream to generate a insertion bitstream that is bit sychronized with the the input bitstream. A bit insertion process (50) then inserts bits into the input bitstream at bit positions indicated by the insertion bitstream. The trigger sequence detection process (40) may be applied to subsequent sections of the input bitstream, as it is not dependent upon the results of the bit insertion process (50).Type: GrantFiled: November 15, 2000Date of Patent: November 16, 2004Assignee: Texas Instruments IncorporatedInventor: Joseph R. Zbiciak
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Patent number: 6757819Abstract: A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result in a selected destination register. A first 32-bit operand (600) is treated as a signed shift value that has a sign and a shift count value. A second operand (602) is shifted by an amount according to the shift count value and in a direction according to the sign of the shift count. One instruction is provided that performs a right shift for a positive shift count and a left shift for a negative shift count, and another instruction is provided performs a left shift for a positive shift count and a right shift for a negative shift count. If the shift count value is greater than 31, then the shift is limited to 31.Type: GrantFiled: October 31, 2000Date of Patent: June 29, 2004Assignee: Texas Instruments IncorporatedInventors: David Hoyle, Richard H. Scales, Min Wang, Joseph R. Zbiciak
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Patent number: 6574724Abstract: A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value.Type: GrantFiled: October 31, 2000Date of Patent: June 3, 2003Assignee: Texas Instruments IncorporatedInventors: David Hoyle, Joseph R. Zbiciak, Jeremiah E. Golston
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Patent number: 6560288Abstract: Variable length codes in a compressed data stream are identified by determining a leading position of a specified value in the compressed data stream. A length of a leading code in the compressed data stream is then determined based on the leading position of the specified value.Type: GrantFiled: December 15, 1999Date of Patent: May 6, 2003Assignee: Texas Instruments IncorporatedInventors: Marcus Alan Gilbert, Joseph R. Zbiciak