Abstract: An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store the results of the tests. The results may be transmitted from the memory device. The integrated memory self-tester may be initiated via a test signal, be self initiated periodically, or be initiated by other means.

Abstract: A memory device having a plurality of multi-bit cells that are programmed with interlaced data provide superior read access time. The multi-bit cells are read by reading the first bit of each of the plurality of cells sequentially using a first reference voltage then reading the second bit of a first subset of the plurality of cells sequentially using a second reference voltage then reading the second bit of a second subset of the plurality of cells sequentially using a third reference voltage. The second reference voltage being higher and the third reference voltage being lower than the first reference voltage.

Abstract: An integrated reliability monitor that automatically tests a memory device until a threshold number of errors has been detected. The integrated reliability monitor eliminates the need for sophisticated external test equipment by automatically testing the memory cells in the memory array and providing the results. An optional programmable registers may store the error threshold value. The programmable registers may also store a time-out value or the reliability monitor may be externally interrupted.

Abstract: A user selectable option to a memory cell, such as a multilevel NAND flash cell, that allows the user to select to optimize programming time or the data integrity. A programmable memory cell can have multiple programming modes. A mode selector can switch the programming of each cell or group of cells between the programming modes. A first programming mode can program the cell with a first programming voltage and maintaining at least a fifty percent of the maximum data margin. A second programming mode can program the cell with a second programming voltage and maintaining at least an eighty five percent of the maximum data margin. The first programming voltage can be greater than the second programming voltage.

Abstract: A method for testing a multi-level memory includes storing multi-level data in a plurality of memory cells of the multi-level memory and reading from configure registers initial values of a plurality of performance variables. The performance variables set operating parameters of the multi-level memory. The method further includes during a first test phase operating the multi-level memory at the initial values of the plurality of performance variables and reading program values of the plurality of performance variables. During a second test phase, the multi-level memory is operated at the program values of the plurality of performance variables.

Abstract: A program/verify method for a multi-level flash memory array, wherein threshold values to be programmed into each flash memory cell are represented using binary bits. In the program/verify method for each cell, the most significant bit representing the threshold level to be programmed into a cell is read first and the cell is programmed to the minimum threshold level represented by the most significant bit. The next most significant bit is then read and if necessary further programming pulses are applied to complete programming. By programming to the level of the most significant bit first rather than programming to each possible threshold separately as determined by all bits read together, less time is required for programming an array.

Abstract: A test methodology for a cache memory subsystem includes setting a test unit to initiate a snoop cycle on a local bus upon lapse of a predetermined delay. The predetermined delay is initially set to a very short delay or a zero delay. The snoop cycle to be executed may take the form of an inquire cycle to a predetermined memory address. The test unit is further set or programmed to begin monitoring the local bus for certain activity including activity which is indicative of whether the snoop cycle occurred. After programming the test unit, the processor core executes a memory operation associated with the address of the snoop cycle. This memory operation causes a cache line transition. At some point, either before, during or after effectuation of the memory operation, the snoop cycle is executed by the test unit in accordance with the predetermined delay. Upon completing the memory operation, a status register is read from the test unit to determine whether the snoop cycle has yet occurred.