Patents by Inventor Joseph T. Pawlowski
Joseph T. Pawlowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105264Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.Type: ApplicationFiled: November 20, 2023Publication date: March 28, 2024Inventors: Mark A. Helm, Joseph T. Pawlowski
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Patent number: 11934705Abstract: Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. The logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.Type: GrantFiled: January 19, 2023Date of Patent: March 19, 2024Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11823742Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.Type: GrantFiled: March 25, 2022Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Mark A Helm, Joseph T. Pawlowski
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Patent number: 11797531Abstract: The present disclosure includes apparatuses, methods, and systems for acceleration of data queries in memory. An example host apparatus includes a controller configured to generate a search key, generate a query for particular data stored in an array of memory cells in a memory device, and send the query to the memory device. The query includes a command to search for the particular data. The query also includes a number of data fields for the particular data including a logical block address (LBA) for the particular data, an LBA offset for the particular data, and a parameter for an amount of bits in data stored in the memory device that do not match corresponding bits in the search key that would result in data not being sent to the host.Type: GrantFiled: August 4, 2020Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Mark A. Helm, Joseph T. Pawlowski
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Patent number: 11727999Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.Type: GrantFiled: March 17, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11714714Abstract: Techniques for non-deterministic operation of a stacked memory system are provided. In an example, a method of operating a memory package can include receiving a plurality of memory access requests for a channel at a logic die, returning first data to a host in response to a first memory access request of the plurality of memory access requests, returning an indication of data not ready to the host in response to a second memory access request of the plurality of memory access requests for second data, returning a first index to the host with the indication of data not ready, returning an indication data is ready with third data in response to a third memory access request of the plurality of memory access requests, and returning the first index with the indication of data ready.Type: GrantFiled: August 22, 2022Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11688477Abstract: Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.Type: GrantFiled: October 15, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11635906Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. An example apparatus includes an array of memory cells and processing circuitry. The processing circuitry is configured to receive, from a host, a query for particular data in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that corresponds more closely to the search key than other data stored in the portions of the array of memory cells, and transfer the data that corresponds more closely to the search key than the other data to the host.Type: GrantFiled: August 4, 2020Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Mark A. Helm, Joseph T. Pawlowski
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Publication number: 20230078205Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.Type: ApplicationFiled: October 26, 2022Publication date: March 16, 2023Inventor: Joseph T. Pawlowski
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Patent number: 11561731Abstract: Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. The logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.Type: GrantFiled: December 18, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Publication number: 20230004305Abstract: Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.Type: ApplicationFiled: September 11, 2022Publication date: January 5, 2023Inventor: Joseph T. Pawlowski
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Publication number: 20220391285Abstract: Techniques for non-deterministic operation of a stacked memory system are provided. In an example, a method of operating a memory package can include receiving a plurality of memory access requests for a channel at a logic die, returning first data to a host in response to a first memory access request of the plurality of memory access requests, returning an indication of data not ready to the host in response to a second memory access request of the plurality of memory access requests for second data, returning a first index to the host with the indication of data not ready, returning an indication data is ready with third data in response to a third memory access request of the plurality of memory access requests, and returning the first index with the indication of data ready.Type: ApplicationFiled: August 22, 2022Publication date: December 8, 2022Inventor: Joseph T. Pawlowski
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Patent number: 11520513Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.Type: GrantFiled: October 20, 2020Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11467979Abstract: Methods, systems, and devices for methods for supporting mismatched transaction granularities are described. A memory system may include a host device the performs data transactions according to a first code word size that is different than a second code word size associated with a storage component within the memory system. A cache may be configured to receive, from the host device, a first code word associated of the first code word size and associated with a first address of the storage component. The cache may store the first code word. When the first code word is evicted from the cache, the memory system may generate a third code word of the second size based on the first code word and a second code word stored in the first address of the storage component and store the third code word at the first address of the storage component.Type: GrantFiled: August 3, 2021Date of Patent: October 11, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11456034Abstract: Methods, systems, and devices for fully associative cache management are described. A memory subsystem may receive an access command for storing a first data word in a storage component associated with an address space. The memory subsystem may include a fully associative cache for storing the data words associated with the storage component. The memory subsystem may determine an address within the cache to store the first data word. For example, the memory subsystem may determine an address of the cache indicated by an address pointer (e.g., based on the order of the addresses) and determine a quantity of accesses associated with the data word stored in that cache address. Based on the indicated cache address and the quantity of accesses, the memory subsystem may store the first data word in the indicated cache address or a second cache address sequential to the indicated cache address.Type: GrantFiled: May 27, 2021Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11455098Abstract: Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.Type: GrantFiled: December 18, 2020Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11422887Abstract: Techniques for non-deterministic operation of a stacked memory system are provided. In an example, a method of operating a memory package can include receiving a plurality of memory access requests for a channel at a logic die, returning first data to a host in response to a first memory access request of the plurality of memory access requests, returning an indication of data not ready to the host in response to a second memory access request of the plurality of memory access requests for second data, returning a first index to the host with the indication of data not ready, returning an indication data is ready with third data in response to a third memory access request of the plurality of memory access requests, and returning the first index with the indication of data ready.Type: GrantFiled: December 18, 2020Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Publication number: 20220215885Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventors: Mark A. Helm, Joseph T. Pawlowski
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Publication number: 20220208284Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.Type: ApplicationFiled: March 17, 2022Publication date: June 30, 2022Inventor: Joseph T. Pawlowski
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Patent number: 11302410Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.Type: GrantFiled: January 8, 2021Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski