Patents by Inventor Joseph Tompkins

Joseph Tompkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Percolation test timer
    Publication number: 20090056420
    Abstract: A device to aid in the testing procedure for soil percolation used in the design of septic systems. The device is used to measure the rapidity of a change of water surface elevation. The device comprises one or more timers (24) connected to a series of sensors so that a change in the presence of water at specific elevations will start or stop a timer. The rate of water absorption and the hydraulic conductivity of the soil are then calculated from the values on the timers.
    Type: Application
    Filed: August 27, 2007
    Publication date: March 5, 2009
    Inventor: David Joseph Tompkins
  • Buffer memory management
    Patent number: 7433904
    Abstract: Various systems and methods for buffer memory management are disclosed. In one embodiment a buffer memory includes at least one queue configured to store a number of buffer access tasks. Buffer reclamation logic is executed to free at least one segment of the buffer memory holding an amount of stale data. Buffer reclamation logic is also included that enables the buffer reclamation logic to submit a buffer access task to the buffer memory based upon a total number of the buffer access tasks stored in the at least one queue.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: October 7, 2008
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Bruce Burns, Michael Tsukernik, Jamie Mulderig, Joseph Tompkins
  • Error correction in a cache memory
    Patent number: 7302619
    Abstract: Various systems and methods for error correction of instructions in an instruction cache coupled to a processor are provided. In one embodiment, a plurality of instructions stored in the instruction cache are fetched for execution by the processor, each of the instructions being fetched during a respective one of a plurality of instruction cycles of the processor. Error detection is performed for each of the instructions concurrently with the fetching of a respective one of the instructions.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: November 27, 2007
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Joseph Tompkins, Duncan Fisher