Patents by Inventor Joseph Tzou
Joseph Tzou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9666255Abstract: A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.Type: GrantFiled: April 22, 2014Date of Patent: May 30, 2017Assignee: Cypress Semiconductor CorporationInventors: Thinh Tran, Joseph Tzou, Jun Li
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Patent number: 9640237Abstract: An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the channels of different groups accessing the memory banks on the different phases of the internal clock signal.Type: GrantFiled: September 25, 2015Date of Patent: May 2, 2017Assignee: Cypress Semiconductor CorporationInventors: Jun Li, Joseph Tzou
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Publication number: 20140340978Abstract: A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.Type: ApplicationFiled: April 22, 2014Publication date: November 20, 2014Applicant: Cypress Semiconductor CorporationInventors: Thinh Tran, Joseph Tzou, Jun Li
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Patent number: 8873264Abstract: A memory device can include a memory array section; a write first-in-first-out circuit (FIFO) configured to transfer write data to the memory array portion; at least one store circuit configured to store a copy of at least a portion of the write data stored in the write FIFO; and an address compare section configured to store write addresses corresponding to the write data of the forwarding circuit.Type: GrantFiled: March 12, 2013Date of Patent: October 28, 2014Assignee: Cypress Semiconductor CorporationInventors: Thinh Tran, Joseph Tzou
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Patent number: 8705310Abstract: A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed.Type: GrantFiled: December 26, 2012Date of Patent: April 22, 2014Assignee: Cypress Semiconductor CorporationInventors: Thinh Tran, Joseph Tzou, Jun Li
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Publication number: 20140056093Abstract: A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed.Type: ApplicationFiled: December 26, 2012Publication date: February 27, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Thinh Tran, Joseph Tzou, Jun Li
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Patent number: 8527802Abstract: A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed.Type: GrantFiled: December 17, 2012Date of Patent: September 3, 2013Assignee: Cypress Semiconductor CorporationInventors: Thinh Tran, Joseph Tzou
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Patent number: 8358557Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period.Type: GrantFiled: September 26, 2011Date of Patent: January 22, 2013Assignee: Cypress Semiconductor CorporationInventors: Joseph Tzou, Thinh Tran, Jun Li
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Patent number: 8149643Abstract: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.Type: GrantFiled: October 23, 2008Date of Patent: April 3, 2012Assignee: Cypress Semiconductor CorporationInventors: Joseph Tzou, Thinh Tran, Jun Li
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Publication number: 20120014202Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time periodType: ApplicationFiled: September 26, 2011Publication date: January 19, 2012Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Joseph Tzou, Thinh Tran, Jun Li
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Patent number: 8095747Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.Type: GrantFiled: September 26, 2008Date of Patent: January 10, 2012Assignee: Cypress Semiconductor CorporationInventors: Bruce Barbara, Gabriel Li, Thinh Tran, Joseph Tzou
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Patent number: 8040164Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.Type: GrantFiled: September 29, 2008Date of Patent: October 18, 2011Assignee: Cypress Semiconductor CorporationInventors: Suresh Parameswaran, Joseph Tzou, Morgan Whately, Thinh Tran
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Patent number: 7719908Abstract: Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory. The match logic circuit may be selectively enabled or disabled.Type: GrantFiled: December 21, 2007Date of Patent: May 18, 2010Assignee: Cypress Semiconductor CorporationInventors: Joseph Tzou, Suresh Parameswaran, Thinh Tran
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Publication number: 20100103762Abstract: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.Type: ApplicationFiled: October 23, 2008Publication date: April 29, 2010Inventors: Joseph Tzou, Thinh Tran, Jun Li
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Publication number: 20100082861Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.Type: ApplicationFiled: September 26, 2008Publication date: April 1, 2010Applicant: Cypress Semiconductor CorporationInventors: Bruce Barbara, Gabriel Li, Thinh Tran, Joseph Tzou
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Patent number: 7684257Abstract: Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable adder unit generating read, accumulate and write output in a single clock cycle. The memory circuit is further configured to minimize data overflow. A high speed accumulation method comprises resetting a memory circuit; reading from an address of the memory circuit; performing internal addition within the memory circuit and rewriting into the address of the memory circuit in a single clock cycle.Type: GrantFiled: December 17, 2007Date of Patent: March 23, 2010Assignee: Cypress Semiconductor CorporationInventors: Christopher Lee, Thinh Tran, Joseph Tzou, Morgan Whately
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Publication number: 20090085614Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.Type: ApplicationFiled: September 29, 2008Publication date: April 2, 2009Inventors: Suresh Parameswaran, Joseph Tzou, Morgan Whately, Thinh Tran
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Patent number: 7403446Abstract: Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally.Type: GrantFiled: September 27, 2005Date of Patent: July 22, 2008Assignee: Cypress Semiconductor CorporationInventors: Suresh Parameswaran, Thinh Tran, Joseph Tzou
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Patent number: 7269772Abstract: An integrated circuit device (200) can include a main portion (204) and a built-in self-test (BIST) portion (204) having outputs coupled to physical input structures (e.g., bond pads) (206) of the integrated circuit device (200). A BIST portion (202) can test timing critical parameters that take into account the effect of input structures (206). A BIST portion (202) can apply BIST test signals with a pipeline structure that can emulate timing parameters, such as a set-up time (Ts) and a clock-to-output time (Tco).Type: GrantFiled: February 23, 2004Date of Patent: September 11, 2007Assignee: Cypress Semiconductor CorporationInventors: Jun Li, Joseph Tzou, Thinh Tran
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Patent number: 7196925Abstract: A memory device can include a group of memory cells, which can be arranged in a column (100) that receives power by way of a first cell supply nodes (106-0 to 106-m). A current limiter (110) can be situated between first cell supply nodes (106-0 to 106-m) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (100). In a particle event, such as an ?-particle strike, a current limiter (110) can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter (110) can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.Type: GrantFiled: August 26, 2004Date of Patent: March 27, 2007Assignee: Cypress Semiconductor CorporationInventors: Joseph Tzou, Jithender Majjiga, Morgan Whately, Thinh Tran