Abstract: A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate. The first and second electrode paddles oppose one another. A sacrificial shorting strap is formed on the substrate. The sacrificial shorting strap connects the first electrode paddle and the second electrode paddle; The tunnel junction is formed connecting the first electrode paddle and the second electrode paddle, after forming the sacrificial shorting strap. The substrate is mounted on a portion of a quantum cavity. The portion of the quantum cavity is placed in a vacuum chamber. The sacrificial shorting strap is etched away in the vacuum chamber while the substrate is mounted to the portion of the quantum cavity, such that the sacrificial shorting strap no longer connects the first and second electrode paddles. The tunnel junction has been protected from electrostatic discharge by the sacrificial shorting strap.

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.

Abstract: A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate. The first and second electrode paddles oppose one another. A sacrificial shorting strap is formed on the substrate. The sacrificial shorting strap connects the first electrode paddle and the second electrode paddle; The tunnel junction is formed connecting the first electrode paddle and the second electrode paddle, after forming the sacrificial shorting strap. The substrate is mounted on a portion of a quantum cavity. The portion of the quantum cavity is placed in a vacuum chamber. The sacrificial shorting strap is etched away in the vacuum chamber while the substrate is mounted to the portion of the quantum cavity, such that the sacrificial shorting strap no longer connects the first and second electrode paddles. The tunnel junction has been protected from electrostatic discharge by the sacrificial shorting strap.

Abstract: Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual III-V semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first III-V semiconductor layer on an oxide; forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer; converting the first III-V semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second III-V semiconductor layer from at least one first active area selective to the first III-V semiconductor layer.

Abstract: A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.

Abstract: Atmospheric particle detectors having a hybrid measurement cavity and light baffle are provided. In one aspect, an atmospheric particle detector includes: an optical measurement cavity; a light baffle attached to the optical measurement cavity, wherein the light baffle is configured to i) permit unobstructed airflow into the optical measurement cavity and ii) block ambient light from entering the optical measurement cavity; a photodetector on a first side of the optical measurement cavity; a retro reflector on a second side of the optical measurement cavity opposite the photodetector, and a light source configured to produce a light beam that passes through the optical measurement cavity without illuminating the photodetector. A method for particle detection using the atmospheric particle detector is also provided.

Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.

Abstract: Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual III-V semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first III-V semiconductor layer on an oxide; forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer; converting the first III-V semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second III-V semiconductor layer from at least one first active area selective to the first III-V semiconductor layer.

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

Abstract: Systems, devices, and methods are provided for detecting and measuring the concentration of non-reactive gases in a given environment, without having to increase the reactivity of the non-reactive gases through thermal heating. For example, a gas sensor device includes a sensing chamber, a chemical getter element disposed in the sensing chamber, and a pressure sensor device. The sensing chamber is configured to capture a gas sample. The chemical getter element is configured to remove reactive gas species of the gas sample through chemical reaction of the reactive gas species with the chemical getter element at room temperature. The pressure sensor device is configured to measure a pressure of non-reactive gas species of the gas sample, which remains in the sensing chamber after removal of the reactive gas species from the sensing chamber. The pressure measurement is used to determine an amount of the non-reactive gas species present in the sample.

Abstract: Atmospheric particle detectors having a hybrid measurement cavity and light baffle are provided. In one aspect, an atmospheric particle detector includes: an optical measurement cavity; a light baffle attached to the optical measurement cavity, wherein the light baffle is configured to i) permit unobstructed airflow into the optical measurement cavity and ii) block ambient light from entering the optical measurement cavity; a photodetector on a first side of the optical measurement cavity; a retro reflector on a second side of the optical measurement cavity opposite the photodetector, and a light source configured to produce a light beam that passes through the optical measurement cavity without illuminating the photodetector. A method for particle detection using the atmospheric particle detector is also provided.

Abstract: A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.

Abstract: A computer-implemented method includes identifying one or more tag readers. The one or more of tag readers are positioned peripherally to a region. The computer-implemented method further includes receiving a signal, by at least one of the one or more tag readers, from a tag. The computer-implemented method further includes determining a received signal strength indication for at least one of the one or more tag readers and mapping at least one received signal strength indication onto at a one dimensional representation of the region to yield a mapped data. The computer-implemented method further includes performing pattern recognition on the mapped data to yield a pattern data and applying machine learning to the pattern data to locate the tag within the region. A corresponding computer system and computer program product are also disclosed.

Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode, the second portion of the second superconductor electrode contacting the substrate on at least one side of the spacer.

Abstract: Methods and systems for detecting emission sites include identifying a set of known emitters having visible features and a spectroscopic signature that correspond to sites that emit a substance to form a training set. A classifier is generated based on the training set. New emitters are identified based on the classifier, a spectroscopic signature map, and a map of visible features. An alert is provided responsive to the identification of a new emitter.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.