Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

Abstract: A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.

Abstract: A method for manufacturing on a substrate a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone in the substrate, thereafter forming the floating gate on the substrate, thereafter extending the floating gate using polysilicon spacers, and thereafter forming the control gate over the floating gate and the polysilicon spacers. Such a semiconductor device may be used in flash memory cells or EEPROMs.

Abstract: A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.

Abstract: A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.

Abstract: There is a method of manufacturing a semiconductor device. In an example embodiment, the method comprises applying a semiconductor substrate that is provided with a conductor at a surface. The conductor has a top surface portion and sidewall portions, of which at least the top surface portion is provided with an etch stop layer comprising silicon carbide. A dielectric layer is applied. A via is etched in the dielectric layer over the conductor and, and stopping on the etch stop layer to create an exposed part of the etch stop layer. Inside the via from at least the top surface portion of the conductor, the exposed part of the etch stop layer is removed. The via is filled with a conductive material.

Abstract: A method of manufacturing an electronic device, a semiconductor device in particular but not exclusively, which method comprises the steps of: