Abstract: Electrical connection to a device region (3,4) of a semiconductor device is formed by providing a semiconductor body (1) having adjacent one major surface (12) a device region (3,4) bounded by an insulating region (19a,19b,9), providing an activating layer (11) on the one major surface (12), applying a flowable material as a layer (13) of photosensitive resist, exposing and developing the resist to define an opening (14) over a contact area (12a) of the device region (3,4), and selectively plating electrically conductive material into the opening (14) to form a conductive pillar (15) in electrical contact with the contatct area (12a). The layer (13) of photosensitive resist is removed after formation of the conductive pillar (15) and a layer of insulating material is then provided to cover the conductive pillar (15) and the surface (12). The insulating layer is then etched to expose a top surface (15a) of the conductive pillar (15).

Abstract: Spaced-apart regions (2) each having top (2a) and side walls (2b) meeting at an edge (20) are defined on a surface (1a) of a substructure (1) forming part of the device. A layer (3) of insulating material is provided over the surface (1a) and regions (2), so that the insulating material is provided preferentially at the edges (20) of the regions (2) to form adjacent the edges (20) portions (31) of the insulating material which overhang the underlying insulating material (32) provided on the surface (1a) and define a void therein. The insulating material layer (3) is then etched anisotropically to expose the top walls (2a).

Abstract: A method of manufacturing a semiconductor device is described in which electrical contact is provided to an area (10) of an electrically conductive level (1) exposed through an opening (2) in a covering layer (3). A further layer is provided over the covering layer (3) as a first layer (4) of one material provided to a first thickness on the covering layer (3) and a second layer (5) of a different material provided to a second thickness on the first layer.

Abstract: A method of enabling electrical connection to a substructure (10) forming part of an electronic device, such as an integrated circuit, is described in which an aluminum-containing electrically conductive level (1) is provided on a surface (12) of the substructure (10), an insulating layer (2) is deposited so as to cover the aluminum-containing electrically conductive level (1), a photosensitive resist layer (3) is provided on the insulating layer and a plasma etching step is then used to etch away insulating material so as to expose an electrically conductive surface to enable electrical connection to be made to the level (1). The insulating material (2) may be etched through a window in the resist layer (3) so as to form a via (14) or the resist layer (3) and insulating material (2) may be etched uniformly to provide a planarized surface.

Abstract: A method is described for providing insulating material on an electrically conductive level (1) of a substructure (10) forming part of an electronic device, which electrically conductive level has at least two spaced-apart electrically conductive regions (1a,1b). Insulating material (2,3) is provided over the electricaly conductive level (1) to a thickness insufficient for insulating material on adjacent conductive regions (1a,1b) to meet thereby leaving a recess (4) in the insulating material between the conductive regions (1a,1b). Next a planarising medium (5) is applied onto the insulating material (2,3) and etched so as to expose a top surface (3a) of the insulating material (2,3) thereby leaving planarising medium (5a) in the recess (4). The insulating material (2,3) is then etched anisotropically using the remaining planarising medium (5a,5b) as a mask so that the surface (11) of the electrically condutive level (1) is exposed.

Abstract: A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the islating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.