Abstract: Non-overlapping cache locations are reserved for each data stream. Therefore, stream information, which is unique to each stream, is used to index the cache memory. Here, this stream information is represented by the stream identification. In particular, a data processing system optimised for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources is provided. An unambiguous stream identification is associated to each of said data stream. Said data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks, wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for controlling said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).

Abstract: The invention provides an integrated circuit comprising a data processing system which performs satisfactorily after integration of the individual building blocks, such as main processors and coprocessors, into the data processing system. This is achieved by measuring the utilization of the communication structure established between the individual building blocks. A measurement unit measures properties of the communication load by observing the communication traffic on connections between processing units and a communication resource, or on connections within the communication resource. The measurement unit performs statistical operations on the observed properties and produces measurement results. The measurement results can be retrieved by measurement software and can be used to modify the data processing system, for example by debugging or by adaptive control.

Abstract: The invention relates to task management in a data processing system, having a plurality of processing elements (CPU, ProcA, ProcB, ProcC). Therefore a data processing system is provided, comprising at least a first processing element (CPU, ProcA, ProcB, ProcC) and a second processing element (CPU, ProcA, ProcB, ProcC) for processing a stream of data objects (DS_Q, DS R, DS S, DST), the first processing element being arranged to pass data objects from the stream of data objects to the second processing element The first and the second processing element are arranged for parallel execution of an application comprising a set of tasks (TP, TA, TB1, TB2, TC), and the first and the second processing element are arranged to be responsive to the receipt of a unique identifier. In order to ensure integrity of data during reconfiguration of the application, the unique identifier is inserted into data stream and passed from one processing element to the other.

Abstract: The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).

Abstract: A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy comprises a higher ranked cache (C1) having a cache controller (CC1) operating according to a write allocate scheme, and a lower ranked cache (C2) is coupled to the higher ranked cache (C1) having a cache controller (CC2). The size of the higher ranked cache is smaller than the size of the lower ranked cache. Both caches (C1, C2) administrate auxiliary information (V1, V2) indicating whether data (D1, D2) present therein is valid. The linesize of the lowerranked cache (C2) is an integer multiple of the linesize of the higher ranked cache (C1). The auxiliary information (V1) in the higher ranked cache (C1) concerns data elements (D1) at a finer granularity than that in the lower ranked cache (C2).

Abstract: Transform based coders are frequently used in digital signal processing. The present invention relates to a method of communicating at least one block of data from a first functional element (3; 4; 7; 12; 14) within a transform based coder (1) or decoder (10) to a second functional element (4; 5; 7; 8; 14; 15) within the coder or decoder, where the block of data comprises a row-column structure of data coefficients. A significant communication workload occurs between individual elements of the coders and decoders.

Abstract: The invention is based on the idea to provide distributed task scheduling in a data processing system having multiple processors. Therefore, a data processing system comprising a first and at least one second processor for processing a stream of data objects, wherein said first processor passes data objects from a stream of data objects to the second processor, and a communication network and a memory is provided. Said second processors are multi-tasking processors, capable of interleaved processing of a first and second task, wherein said first and second tasks process a first and second stream of data objects, respectively. Said data processing system further comprises a task scheduling means for each of said second processors, wherein said task scheduling means is operatively arranged between said second processor and said communication network, and controls the task scheduling of said second processor.