Abstract: Memory systems and methods of making the same are described. In one aspect, a memory system may includes multiple memory layers that may be identical when manufactured and may be readily customized before or after the layers are arranged into a three-dimensional stack so that data may be sent to or retrieved from individual layers (either serially or in parallel) independently of the other layers.

Abstract: A level of a solid state memory device includes main memory and address logic. The address logic includes first and second groups of address elements. Current-carrying capability of the first group of address elements is greater than current-carrying capability of the second group of address elements. Current flowing through the address elements during programming causes the resistance states of only the second group of address elements to change.

Abstract: A memory device includes write-once memory; non-volatile memory; and a circuit for writing user data to the write-once memory and at least one of user data and error correction data to the non-volatile memory.

Abstract: A multiplexer includes a plurality of stages. Each stage includes a storage device coupled to a data output; a first diode coupled between a data input and a power supply input; and a second diode coupled between the power supply input and the data output.

Abstract: A set of address elements is configured by assigning a set of constant weight code words satisfying inequality (2 w+t+1)≦n, where w is the weight of the code words, n is the number of address lines, and t is the maximum allowable number of defective address lines.

Abstract: A level of a solid state memory device includes main memory and address logic. The address logic is programmed by causing current to flow through an address element of the logic; and irradiating the address element so that the address element changes resistance states.

Abstract: A solid state memory device is fabricated by forming a level of the device; identifying defective areas in the level; and programming address logic of the level to avoid the defective areas in the level.

Abstract: A level of a solid state memory device includes main memory and address logic. The address logic is programmed by causing current to flow through an address element of the logic; and irradiating the address element so that the address element changes resistance states.

Abstract: A level of a solid state memory device includes main memory and address logic. The address logic includes first and second groups of address elements. Current-carrying capability of the first group of address elements is greater than current-carrying capability of the second group of address elements. Current flowing through the address elements during programming causes the resistance states of only the second group of address elements to change.

Abstract: Systems and methods that enable the state of a memory cell to be determined with greater accuracy are described. In one memory cell sensing approach, a memory cell is addressed, an input signal is applied to the addressed memory cell over a range of values, and the state of the memory cell is read based upon a discontinuity in a sensed electrical response to the applied input signal values.

Abstract: A method involves the use of a sequence of address configurations covering L memory lines and n address lines. The method includes forming L blocks. A most significant column of each block is filled with the sequence such that the most significant column of each block contains the same unshifted sequence. A least significant column of each block is filled with the sequence such entries in the least significant column of the blocks are shifted cyclically. The L blocks contain address configurations for L2 memory lines and 2n address lines.

Abstract: A set of address elements is configured by assigning a set of address configurations having a symmetric distance of at least t+1, where t is the maximum allowable number of defective address lines.

Abstract: This invention provides a means for high data multiple wavelength encoding with reduced bandwidth requirements by combining the outputs of a plurality of multiple wavelength processing modules. Each module produces a modulated optical pulse train with the pulses from each module being phase offset with respect to each other. The phase offsets are controlled by a feedback system, such that when combined, the plurality of multiple wavelength processing modules produce a high data rate sequence of substantially non-overlapping optical pulses at multiple wavelengths. The invention is compatible with highly integrated optical and electronic modules and because the wavelength processing modules are identical, additional spare modules can be included to provide redundancy.

Abstract: An electrically addressable device for recording, addressing and reading of data, includes a storage array unit having multiple layers of data storage medium. An electrical marking device is disposed on at least one of the layers of storage medium of the storage array unit to provide a display indicating any pre-selected information, such as the nature of the content of the data stored on the storage array unit. The electrical marking device may comprise at least one layer functioning as a display layer that is partially visually altered to provide a display of information, such as to display the subject matter and name of the content of the data and the amount of memory storage that has been used. The display layer comprises a plurality of information storage cells, each representing the value of at least one data bit, wherein the visual appearance of each of the information storage cell is varied depending on the value of the data bit.

Abstract: Systems and methods that enable the state of a memory cell to be determined with greater accuracy are described. In one memory cell sensing approach, a memory cell is addressed, an input signal is applied to the addressed memory cell over a range of values, and the state of the memory cell is read based upon a discontinuity in a sensed electrical response to the applied input signal values.

Abstract: This invention provides a means for generating multiple wavelengths in an integrated manner using a resonant cavity containing dispersion shifted non-linear medium and coupled to a pulsed laser source. The dispersion shifted non-linear medium is seeded by at least some of the desired wavelengths. The laser source emits radiation at a particular wavelength and is pulsed in a manner synchronously related to the round trip time of the resonant cavity. By means of wave mixing, such as four wave mixing, the dispersion shifted non-linear medium produces a set of discrete wavelengths. The reflective elements of the resonant cavity are designed to contain the radiation of the laser sources within the resonant cavity and to transmit an equal amount of each of the generated set of wavelengths.

Abstract: This invention provides a means for generating multiple wavelengths in an integrated manner using a resonant cavity containing dispersion shifted medium and coupled to at least one pulsed laser source. The laser sources emit radiation at a particular wavelength and are pulsed in a manner synchronously related to the round trip time of the resonant cavity. The dispersion shifted medium is designed to produce a set of discrete wavelengths, by such means as four wave mixing, whose frequencies are related to the wavelength of the pulsed laser sources and the repetition frequency of the resonant cavity. The reflective elements of the resonant cavity are designed to contain the radiation of the laser sources within the resonant cavity and to transmit an equal amount of each of the generated set of wavelengths.

Abstract: A drive such as a DVD-ROM drive encrypts an error code correction (ECC) block in a manner that still retains the error correction capabilities of the ECC block. Encryption is performed by generating an encryption mask including a plurality of random numbers and redundancy data. The encryption mask is bitwise XOR'ed with the ECC block. The product of the bitwise XOR is an encrypted ECC block, which can then be transmitted over an unsecured bus to a host processor. The integrity of the ECC codewords is preserved. This allows the host processor to perform some or all error correction on the encrypted ECC block. Error correction can be removed from the drive altogether, or error correction can be performed by the drive and additionally by the host processor, if necessary. User data in the ECC block can be XOR'ed entirely with random numbers, or the user data can be XOR'ed selectively with random numbers and zeros to selectively encrypt a portion of the user data.

Abstract: A drive such as a DVD-ROM drive encrypts an error code correction (ECC) block in a manner that still retains the error correction capabilities of the ECC block. Encryption is performed by generating an encryption mask including a plurality of random numbers and redundancy data. The encryption mask is bitwise XOR'ed with the ECC block. The product of the bitwise XOR is an encrypted ECC block, which can then be transmitted over an unsecured bus to a host processor. The integrity of the ECC codewords is preserved. This allows the host processor to perform some or all error correction on the encrypted ECC block. Error correction can be removed from the drive altogether, or error correction can be performed by the drive and additionally by the host processor, if necessary. User data in the ECC block can be XOR'ed entirely with random numbers, or the user data can be XOR'ed selectively with random numbers and zeros to selectively encrypt a portion of the user data.

Abstract: Two different (d,k)-RLL codes can be used in systems such as erasable and writable dense optical disks. This is because it is typically possible to make readers capable of reading information written at a higher resolution (by a short wavelength authoring system) than the resolution that can be written by a consumer writer (using a laser of the same or longer wavelength as the reader). For one embodiment, two different decoders are used to decode the data. Alternately, we present an encoding scheme which operates with a single decoder. In one case, q1=q2 (and as a result p1<p2), so that the decoders D1 and D2 actually process blocks of the same length. The decoding of the sequences encoded by E1 is done using the decoder D2 plus an additional function &psgr; which maps the restored p2-blocks into p1-blocks in a to very simple manner. This way, we do not need a separate circuit for the (d1,k1)-RLL decoder, because D1 is obtained as a cascading of D2 and another very simple circuit &psgr;.