Patents by Inventor Joshua Bell

Joshua Bell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070038927
    Abstract: Systems and/or methods (“tools”) are described that convert or present conversion problems for electronic documents. The tools may convert a generally unstructured electronic document to a generally structured electronic document using non-visual textual and layout information of the unstructured document. The tools can also present possible problems with this or other types of conversion. And the tools can enable a user to alter an electronic document's schema without altering its visual layout.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 15, 2007
    Applicant: Microsoft Corporation
    Inventors: Nicholas Dallett, Scott Roberts, Brian Teutsch, Jun Jin, Willson David, Joshua Bell, David Snow, Aleksandr Tsybert, Shuk-Yan Lai
  • Publication number: 20070036433
    Abstract: Systems and/or methods (“tools”) are described that enable a recognition system to recognize user-entered data conforming to a data rule. The tools may do so by providing data regions for a document. With these data regions, the recognition system may better determine what information on the document is user-entered and what is not. Each of these data regions has a data rule governing data for that region. With the data rule, the recognition system may better recognize data from each region. The tools may ascertain these data regions and rules from an electronic form having controls laid out similarly to data-entry areas of the document.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 15, 2007
    Applicant: Microsoft Corporation
    Inventors: Brian Teutsch, Willson David, Joshua Bell, Aleksandr Tsybert, Laurent Mollicone
  • Publication number: 20060226721
    Abstract: The invention includes an electric alternator/motor having a rotor, stator and at least one winding in the stator adapted to conduct a current, the machine also having and first and second magnetic circuits one of which includes a saturable portion in which saturation may be controlled to permit control of the machine
    Type: Application
    Filed: May 26, 2006
    Publication date: October 12, 2006
    Inventors: Kevin Dooley, Joshua Bell
  • Publication number: 20060197982
    Abstract: Systems and/or methods that enable addition of a designer-created aspect originating from one electronic form template into another electronic form template are described. The systems and/or methods may also, in one embodiment, enable a user to graphically package designer-created aspects of an existing electronic form template into a component capable of being added to another electronic form template. In another embodiment, these systems and/or methods may enable mapping of an existing non-structural designer-created aspect originating from one electronic form template onto a data structure of another electronic form template.
    Type: Application
    Filed: March 4, 2005
    Publication date: September 7, 2006
    Applicant: Microsoft Corporation
    Inventors: Joshua Bell, Scott Roberts, Jun Jin, Brian Teutsch, Laurent Mollicone
  • Patent number: 6936948
    Abstract: The invention includes an electric machine having a rotor, stator and at least one winding in the stator adapted to conduct a current, and a secondary winding, electrically isolated from the first winding and inductively coupled to the first winding, which may be used to control at least one of the output voltage and current of the first winding.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: August 30, 2005
    Assignee: Pratt & Whitney Canada Corp.
    Inventors: Joshua Bell, Kevin Allan Dooley
  • Patent number: 6904561
    Abstract: A system and method for graphically showing the order and timing of elements in a presentation program or other software. The sequence of events is shown in an event list, a list of events in sequence order, each event being associated with an event timeline bar and correlated with a universal timeline, in the editing window of an electronic presentation or other software that deals with the scheduling of events. In one embodiment, each item in the list represents an individual animation effect. Elements of the event list are logically related to each other and these logical relationships may be used in assisting a user to build a sequence of events (e.g., an animation sequence).
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: June 7, 2005
    Assignee: Microsoft Corp.
    Inventors: Peter Faraday, Joshua Bell, Steven P. Geffner
  • Publication number: 20050097471
    Abstract: A system and method for graphically showing the order and timing of elements in a presentation program or other software. The sequence of events is shown in an event list, a list of events in sequence order, each event being associated with an event timeline bar and correlated with a universal timeline, in the editing window of an electronic presentation or other software that deals with the scheduling of events. In one embodiment, each item in the list represents an individual animation effect. Elements of the event list are logically related to each other and these logical relationships may be used in assisting a user to build a sequence of events (e.g., an animation sequence).
    Type: Application
    Filed: November 24, 2004
    Publication date: May 5, 2005
    Applicant: Microsoft Corporation
    Inventors: Peter Faraday, Joshua Bell, Steven Geffner
  • Publication number: 20040239203
    Abstract: The invention includes an electric machine having a rotor, stator and at least one winding in the stator adapted to conduct a current, and a secondary winding, electrically isolated from the first winding and inductively coupled to the first winding, which may be used to control at least one of the output voltage and current of the first winding.
    Type: Application
    Filed: December 22, 2003
    Publication date: December 2, 2004
    Inventors: Joshua Bell, Kevin Allan Dooley
  • Patent number: 6766498
    Abstract: A method, system and computer program product for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (“interconnections of interest”). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mahesh S. Sharma, David M. Newmark, Teja Singh, Joshua A. Bell
  • Publication number: 20040044974
    Abstract: A method, system and computer program product for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (“interconnections of interest”). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 4, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mahesh S. Sharma, David M. Newmark, Teja Singh, Joshua A. Bell