Abstract: Inversely proportional voltage-delay buffers for buffering data according to data voltage levels are disclosed. In one aspect, an inversely proportional voltage-delay buffer is configured to buffer a data signal for an amount of time that is inversely proportional to a voltage level of the data signal. The inversely proportional voltage-delay buffer includes an inversion circuit and pass circuit. The inversion circuit is configured to generate a control signal that is the logic inverse of the data signal. Notably, the control signal transitions at a rate proportional to the voltage level of the data signal. The pass circuit is configured to generate a weak logic state of the data signal when the data signal and the control signal have the same logic state. The pass circuit is configured to generate a strong logic state of the data signal when the data input and the control signal have opposite logic states.

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

Abstract: Inversely proportional voltage-delay buffers for buffering data according to data voltage levels are disclosed. In one aspect, an inversely proportional voltage-delay buffer is configured to buffer a data signal for an amount of time that is inversely proportional to a voltage level of the data signal. The inversely proportional voltage-delay buffer includes an inversion circuit and pass circuit. The inversion circuit is configured to generate a control signal that is the logic inverse of the data signal. Notably, the control signal transitions at a rate proportional to the voltage level of the data signal. The pass circuit is configured to generate a weak logic state of the data signal when the data signal and the control signal have the same logic state. The pass circuit is configured to generate a strong logic state of the data signal when the data input and the control signal have opposite logic states.

Abstract: A method and apparatus for reading bitcell data stored in a content addressable memory (CAM) includes controlling a first compare line of a first column of an array of bitcells to a first logic state while controlling a second compare line of the first column as well as first and second compare lines of each of the other columns of the array to a second logic state during a second mode of operation, in order to provide the bitcell data stored in at least one bitcell of the first column to a respective match line. The method also includes reading the bitcell data on the respective match line.

Abstract: Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit. The different characteristics of the circuit elements may cause a keeper circuit to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor in a pull down or discharge path. An adaptive keeper circuit, however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit matches the behavior of the pull down path and prevents the pull down path from erroneously changing the logical state stored by the dynamic circuit.

Abstract: Inversely proportional voltage-delay buffers for buffering data according to data voltage levels are disclosed. In one aspect, an inversely proportional voltage-delay buffer is configured to buffer a data signal for an amount of time that is inversely proportional to a voltage level of the data signal. The inversely proportional voltage-delay buffer includes an inversion circuit and pass circuit. The inversion circuit is configured to generate a control signal that is the logic inverse of the data signal. Notably, the control signal transitions at a rate proportional to the voltage level of the data signal. The pass circuit is configured to generate a weak logic state of the data signal when the data signal and the control signal have the same logic state. The pass circuit is configured to generate a strong logic state of the data signal when the data input and the control signal have opposite logic states.

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

Abstract: Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit. The different characteristics of the circuit elements may cause a keeper circuit to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor in a pull down or discharge path. An adaptive keeper circuit, however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit matches the behavior of the pull down path and prevents the pull down path from erroneously changing the logical state stored by the dynamic circuit.

Abstract: At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source.

Abstract: A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.

Abstract: Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce output load, reducing power consumption. In certain embodiments, SRAM includes an SRAM array. The SRAM includes a global bitline circuit for each SRAM array column. Each global bitline circuit includes memory access circuit that pre-charges local bitlines corresponding to bitcells in SRAM array. The data read from selected bitcell is read from its local bitline onto aggregated read bitline, an aggregation of local bitlines. The SRAM includes bitline evaluation circuit that sends data from aggregated read bitline onto global bitline. Instead of sending data based on rising transition of clock trigger, data is sent onto the global bitline based on falling transition of clock trigger. A global bitline scheme can be employed that reduces glitches and resulting increases in power consumption.