Abstract: Analog counter circuits, read-out integrated circuits, and infrared detector devices are disclosed. In one embodiment, an analog counter circuit includes a first capacitor including a first terminal and a second terminal, a switch electrically coupled the first capacitor and a first voltage input, a field effect transistor, and a second capacitor. Setting the switch to an on-state pre-charges the first capacitor such that a voltage at the second terminal of the first capacitor is the first voltage. Applying a charge voltage at a charge input further charges the first capacitor. When a voltage at the second terminal of the first capacitor is greater than a threshold voltage of the field effect transistor, the field effect transistor turns on and transfers a charge on the first capacitor to the second capacitor.

Abstract: A method of digitally boresighting includes finding a laser spot in a field of view of an imaging device that has an optical center, wherein the laser spot is generated by a laser, determining an offset vector between the laser spot in the field of view and the optical center, and correcting for boresight misalignment of the laser and imaging device in the image on a display using the offset vector.

Abstract: A pixel output processing circuit of a focal plane array (FPA) having a plurality of laser range finding pixels (LRF) is provided. The respective LRF pixels output a high frequency analog signal in response to sensing a reflected laser pulse. The pixel output processing circuit includes a common net and a detection circuit. The common net is connected to a amplifying transistor of each of the LRF pixels for receiving analog signals output from the respective LRF pixels. The detection circuit is coupled to the common net and outputs a pulse flag in response to detecting that a high frequency analog signal has been received by the common net.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: An imaging method includes assigning pixels within the extent of a focal plane array active area to a first readout range and a second readout range. Image data is read out from the pixels assigned to the first readout range and the second readout range. Pixels located within the extend of the focal plane array active area and not assigned to the first readout range or the second readout range are left unread. Imaging systems and hyperspectral imaging arrangements are also described.

Abstract: A multimode pixel of a pixel array is provided. The multimode pixel includes a photodetector, an image sensing circuit having a first plurality of transistors, and a laser range finding (LRF) circuit having a second plurality of transistors. At least one transistor of the second plurality of transistors, but not all of the second plurality of transistors, is included in the first plurality of transistors. The LRF circuit being configured to perform LRF operations and the image sensing circuit is configured to perform passive imaging operations. The image sensing circuit and the LRF circuit are configured to perform concurrently.

Abstract: A pixel of a pixel array is provided. The pixel includes a low frequency path configured to receive an input signal from a corresponding photodetector. The low frequency path includes a passive imaging circuit provided along the low frequency path, the passive imaging circuit configured to output an analog imaging signal and a flash analog to digital converter (ADC) that receives the analog imaging signal and processes the analog imaging signal to output a coarse digitized signal.

Abstract: A configurable analog to digital converter (ADC) is provided. The configurable ADC includes a comparator receiving and comparing a first analog voltage signal to a second analog voltage signal V-DAC and outputting a signal C-OUT that is responsive to a result of the comparison, an integrator operating on C-OUT and outputting an N-bit value, a digital-to analog converter (DAC) converting the N-bit value to the second analog voltage signal V-DAC, and an integrator, the integrator including the N-bit memory, which is coupled to an arithmetic logic unit (ALU), the N-bit memory and ALU cooperating to perform operations using both the N-bit value and C-OUT. The configurable ADC is configured to operate in more than one mode selected from a plurality of selectable ADC modes.

Abstract: A photodiode includes an absorption layer. A cap layer is disposed on a surface of the absorption layer. A pixel diffusion area within the cap layer extends beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons therefrom. A mesa trench is defined through the cap layer surrounding the pixel diffusion area, wherein the mesa trench defines a floor at the surface of the absorption layer and opposed sidewalls extending away from the surface of the absorption layer. An implant is aligned with the mesa trench and extends from the floor of the mesa trench through the absorption layer surrounding a portion of the absorption layer proximate the pixel diffusion area.

Abstract: A photodiode includes an absorption layer. A cap layer is disposed on a surface of the absorption layer. A pixel diffusion area within the cap layer extends beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons therefrom. A mesa trench is defined through the cap layer surrounding the pixel diffusion area, wherein the mesa trench defines a floor at the surface of the absorption layer and opposed sidewalls extending away from the surface of the absorption layer. An implant is aligned with the mesa trench and extends from the floor of the mesa trench through the absorption layer surrounding a portion of the absorption layer proximate the pixel diffusion area.

Abstract: A method of correcting lag in an imaging pixel includes receiving a current frame pixel value and determining a current filter coefficient using the current frame pixel value. A pixel output is determined from a product of the current frame pixel value and current frame filter coefficient. The product of a first prior frame pixel value and corresponding first prior frame filter coefficient is added to the pixel output to generate a corrected pixel output to more closely indicates incident illumination on the imaging pixel during an integration period from which the current frame pixel value was obtained.

Abstract: A configurable analog to digital converter (ADC) is provided. The configurable ADC includes a comparator receiving and comparing a first analog voltage signal to a second analog voltage signal V-DAC and outputting a signal C-OUT that is responsive to a result of the comparison, an integrator operating on C-OUT and outputting an N-bit value, a digital-to analog converter (DAC) converting the N-bit value to the second analog voltage signal V-DAC, and an integrator, the integrator including the N-bit memory, which is coupled to an arithmetic logic unit (ALU), the N-bit memory and ALU cooperating to perform operations using both the N-bit value and C-OUT. The configurable ADC is configured to operate in more than one mode selected from a plurality of selectable ADC modes.

Abstract: A pixel of a pixel array is provided. The pixel includes a low frequency path configured to receive an input signal from a corresponding photodetector. The low frequency path includes a passive imaging circuit provided along the low frequency path, the passive imaging circuit configured to output an analog imaging signal and a flash analog to digital converter (ADC) that receives the analog imaging signal and processes the analog imaging signal to output a coarse digitized signal.

Abstract: An imaging method includes assigning pixels within the extent of a focal plane array active area to a first readout range and a second readout range. Image data is read out from the pixels assigned to the first readout range and the second readout range. Pixels located within the extend of the focal plane array active area and not assigned to the first readout range or the second readout range are left unread. Imaging systems and hyperspectral imaging arrangements are also described.

Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

Abstract: A method of digitally boresighting includes finding a laser spot in a field of view of an imaging device that has an optical center, wherein the laser spot is generated by a laser, determining an offset vector between the laser spot in the field of view and the optical center, and correcting for boresight misalignment of the laser and imaging device in the image on a display using the offset vector.

Abstract: A method includes acquiring a pulse detection bitmap from an imaging sensor array into a digital read out integrated circuit (DROIC), filtering the pulse detection bitmap within the DROIC to convert the pulse detection bitmap into a filtered pulse detection bitmap, and determining for a given pixel in the filtered pulse detection bitmap whether the pixel has a value that exceeds a threshold, indicating a true laser pulse return has been detected in the pixel.

Abstract: A pixel output processing circuit of a focal plane array (FPA) having a plurality of laser range finding pixels (LRF) is provided. The respective LRF pixels output a high frequency analog signal in response to sensing a reflected laser pulse. The pixel output processing circuit includes a common net and a detection circuit. The common net is connected to a amplifying transistor of each of the LRF pixels for receiving analog signals output from the respective LRF pixels. The detection circuit is coupled to the common net and outputs a pulse flag in response to detecting that a high frequency analog signal has been received by the common net.