Patents by Inventor Joshua Rubin
Joshua Rubin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240179497Abstract: Example systems, methods, and computer-readable media are disclosed. In an example method, a first outbound text message is transmitted via a message broker of a messaging platform from a client to a plurality of recipients. In response to the first outbound message, a plurality of inbound text messages is received, via the message broker, from the plurality of recipients. A first grouping of the plurality of inbound text messages is determined, the first grouping associated with one or more recipients of the plurality of recipients. The first grouping is presented to the client. A second outbound text message is transmitted, via the message broker, from the client to the one or more recipients of the plurality of recipients. The second outbound text message is generated based on the first grouping. The message broker is in communication with a first messaging service and a second messaging service different from the first messaging service.Type: ApplicationFiled: September 5, 2023Publication date: May 30, 2024Applicant: Community.com, Inc.Inventors: Alec RUBIN, Skylar KERZNER, Nate SALETAN, Lars PERKINS, Barry STEINGLASS, Joshua ROSENHECK, Tomas KOCI, Matthew PELTIER
-
Patent number: 11276576Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.Type: GrantFiled: November 12, 2019Date of Patent: March 15, 2022Assignee: International Business Machines CorporationInventors: Junli Wang, Alexander Reznicek, Shogo Mochizuki, Joshua Rubin
-
Patent number: 11177217Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: GrantFiled: January 9, 2020Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
-
Patent number: 11081542Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.Type: GrantFiled: December 11, 2019Date of Patent: August 3, 2021Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten, Joshua Rubin
-
Patent number: 10804204Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.Type: GrantFiled: August 28, 2019Date of Patent: October 13, 2020Assignee: International Business Machines CorporationInventors: Joshua Rubin, Lawrence A. Clevenger, Charles L. Arvin
-
Patent number: 10727139Abstract: Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.Type: GrantFiled: January 4, 2019Date of Patent: July 28, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Terry Hook, Ardasheir Rahman, Joshua Rubin, Chen Zhang
-
Patent number: 10679890Abstract: Structures and methods for making nanosheet structures with an electrically isolating feature associated therewith. The structure includes: a substrate, an epitaxial oxide layer over the substrate, a plurality of stacked nanosheets of semiconductor channel material over the epitaxial layer, and a source/drain semiconductor material located laterally adjacent and on each side of the plurality of stacked nanosheets of semiconductor channel material, where the plurality of nanosheets are decoupled from the source/drain semiconductor material by the epitaxial oxide layer.Type: GrantFiled: February 1, 2018Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Xin Miao, Joshua Rubin
-
Publication number: 20200144187Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
-
Publication number: 20200119136Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten, Joshua Rubin
-
Publication number: 20200083051Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Inventors: Junli Wang, Alexander Reznicek, Shogo Mochizuki, Joshua Rubin
-
Patent number: 10580738Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: GrantFiled: March 20, 2018Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
-
Patent number: 10573521Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.Type: GrantFiled: January 30, 2018Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junli Wang, Alexander Reznicek, Shogo Mochizuki, Joshua Rubin
-
Publication number: 20200035603Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.Type: ApplicationFiled: July 24, 2018Publication date: January 30, 2020Inventors: Joshua Rubin, Lawrence A. Clevenger, Charles L. Arvin
-
Publication number: 20200035604Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.Type: ApplicationFiled: August 28, 2019Publication date: January 30, 2020Inventors: Joshua Rubin, Lawrence A. Clevenger, Charles L. Arvin
-
Patent number: 10546915Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.Type: GrantFiled: December 26, 2017Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten, Joshua Rubin
-
Patent number: 10535608Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.Type: GrantFiled: July 24, 2018Date of Patent: January 14, 2020Assignee: International Business Machines CorporationInventors: Joshua Rubin, Lawrence A. Clevenger, Charles L. Arvin
-
Publication number: 20190295952Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: ApplicationFiled: March 20, 2018Publication date: September 26, 2019Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
-
Publication number: 20190237336Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.Type: ApplicationFiled: January 30, 2018Publication date: August 1, 2019Inventors: Junli Wang, Alexander Reznicek, Shogo Mochizuki, Joshua Rubin
-
Publication number: 20190237360Abstract: Structures and methods for making nanosheet structures with an electrically isolating feature associated therewith. The structure includes: a substrate, an epitaxial oxide layer over the substrate, a plurality of stacked nanosheets of semiconductor channel material over the epitaxial layer, and a source/drain semiconductor material located laterally adjacent and on each side of the plurality of stacked nanosheets of semiconductor channel material, where the plurality of nanosheets are decoupled from the source/drain semiconductor material by the epitaxial oxide layer.Type: ApplicationFiled: February 1, 2018Publication date: August 1, 2019Inventors: Alexander REZNICEK, Xin MIAO, Joshua RUBIN
-
Publication number: 20190221484Abstract: Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Inventors: Terry Hook, Ardasheir Rahman, Joshua Rubin, Chen Zhang