Abstract: A system for porting code from a native platform to a non-native platform is provided which utilizes a non-native, platform-specific layer of code and a platform-neutral layer of code. The platform-neutral layer substantially emulates the native platform of ported code and provides a platform-neutral interface to the ported code. Together, the platform-specific layer and the platform-neutral layer provide an execution environment in which the ported code operates as a kernel extension of the non-native platform. The platform-neutral layer of the execution environment is portable to other non-native platforms so that code can be ported to another non-native platform by replacing the platform-specific layer with a customized platform-specific layer, which is adapted to the other non-native platform.

Abstract: A method of porting code from a native platform to a non-native platform is provided which utilizes a non-native, platform-specific layer of code and a platform-neutral layer of code. The platform-neutral layer substantially emulates the native platform of ported code and provides a platform-neutral interface to the ported code. Together, the platform-specific layer and the platform-neutral layer provide an execution environment in which the ported code operates as a kernel extension of the non-native platform. The platform-neutral layer of the execution environment is portable to other non-native platforms so that code can be ported to another non-native platform by replacing the platform-specific layer with a customized platform-specific layer, which is adapted to the other non-native platform.

Abstract: In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does speculative prefetching, or it can arise from a multiplicity of processors in a shared-bus configuration.

Abstract: A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second instruction set architecture. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first branch history table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second branch history table.The first instruction set architecture may be system level instructions and the second instruction set architecture may be millicode instructions that, for example, define a complex system level instruction and/or emulate a third instruction set architecture.

Abstract: Monitoring apparatus is provided to allow out-of-sequence fetching of operands while preserving the appearance of in-sequence fetching to the processor of a computer. The key elements include a stack (119) of N entries holding the addresses of the last M, where M is less than or equal to N, out-of-sequence fetches. A comparator (103) is provided for comparing addresses in the stack with a test address. This test address is supplied via an OR gate (107) as either store addresses or cross-invalidate addresses, the latter being for a multiprocessor system. The addresses in the stack that compare with the test address are set as invalid. In addition, all addresses in the stack are set as invalid on the occurrence of a cache miss or serializing instruction. Finally, a select and check entry function (113) associates an address in the stack with the instruction it represents and deletes the address from the stack when the instruction is handled in its proper sequence.

Abstract: Apparatus for fetching instructions in a computing system. A broadband branch history table is organized by cache line. The broadband branch history table determines from the history of branches the next cache line to be referenced and uses that information for prefetching lines into the cache.