Patents by Inventor Joungin Yang
Joungin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110254172Abstract: A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Inventors: DongSam Park, JoungIn Yang
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Patent number: 8035210Abstract: A method of manufacture of an integrated circuit package system includes: providing a base substrate; coupling a base integrated circuit on the base substrate; forming a double side molded interposer unit over the base integrated circuit including: providing an interposer substrate having an interposer top and an interposer bottom, mounting a first integrated circuit to the interposer bottom and electrically connected thereto, mounting a second integrated circuit to the interposer top and electrically connected thereto, and molding a first chip cover on the first integrated circuit and a second chip cover on the second integrated circuit; and coupling an external component to the double side molded interposer unit.Type: GrantFiled: December 28, 2007Date of Patent: October 11, 2011Assignee: STATS ChipPAC Ltd.Inventors: Joungin Yang, Dongjin Jung, In Sang Yoon
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Patent number: 7986048Abstract: A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings.Type: GrantFiled: February 18, 2009Date of Patent: July 26, 2011Assignee: Stats Chippac Ltd.Inventors: DongSam Park, JoungIn Yang
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Publication number: 20110147906Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated interconnect pad; attaching an embedded interconnect to the plated interconnect pad; and forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side and the plated interconnect pad and the adhesive exposed from the encapsulation second side.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Inventors: JoungIn Yang, YoungSik Cho, SungHyun Lee
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Patent number: 7901987Abstract: A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors.Type: GrantFiled: March 19, 2008Date of Patent: March 8, 2011Assignee: Stats Chippac Ltd.Inventors: Joungin Yang, Dongjin Jung
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Publication number: 20110024890Abstract: A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate.Type: ApplicationFiled: September 15, 2010Publication date: February 3, 2011Applicant: STATS CHIPPAC, LTD.Inventors: JoungIn Yang, ChoongBin Yim, KeonTeak Kang, YoungChul Kim
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Patent number: 7804166Abstract: An integrated circuit package system includes: providing a module substrate having dimension predetermined for attachment adjacent a device; attaching a module die adjacent the module substrate; and applying a module molding material cantilevered from the module substrate and over the module die.Type: GrantFiled: March 24, 2008Date of Patent: September 28, 2010Assignee: Stats Chippac Ltd.Inventors: Joungin Yang, YoungSik Cho, Nam Ju Cho
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Publication number: 20100237482Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.Type: ApplicationFiled: March 20, 2009Publication date: September 23, 2010Inventors: JoungIn Yang, Dongjin Jung, DongSam Park
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Patent number: 7800211Abstract: A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical contact with the first semiconductor die through a first adhesive, such as a film on wire adhesive. A second DSM ISM is in physical contact with the first DSM ISM through a second adhesive. The arrangement of the first and second DSM ISM reduce headroom requirements for the package and increase device packing density. Each DSM ISM has semiconductor die disposed in cavities. An interposer is disposed above the top DSM ISM. Wire bonds connect the semiconductor die and DSM ISMs to the solder balls. An encapsulant surrounds the first semiconductor die and first DSM ISM with an exposed mold area in the encapsulant above the interposer.Type: GrantFiled: June 29, 2007Date of Patent: September 21, 2010Assignee: STATS ChipPAC, Ltd.Inventors: JoungIn Yang, ChoongBin Yim, KeonTeak Kang, YoungChul Kim
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Publication number: 20100207262Abstract: A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings.Type: ApplicationFiled: February 18, 2009Publication date: August 19, 2010Inventors: DongSam Park, JoungIn Yang
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Publication number: 20090236718Abstract: A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Inventors: Joungin Yang, Dongjin Jung
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Publication number: 20090236754Abstract: An integrated circuit package system includes: providing a module substrate having dimension predetermined for attachment adjacent a device; attaching a module die adjacent the module substrate; and applying a module molding material cantilevered from the module substrate and over the module die.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Inventors: Joungin Yang, YoungSik Cho, Nam Ju Cho
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Publication number: 20090166835Abstract: An integrated circuit package system including: providing a base substrate; coupling a base integrated circuit on the base substrate; forming a double side molded interposer unit over the base integrated circuit including: providing an interposer substrate having an interposer top and an interposer bottom, mounting a first integrated circuit to the interposer bottom and electrically connected thereto, mounting a second integrated circuit to the interposer top and electrically connected thereto, and molding a first chip cover on the first integrated circuit and a second chip cover on the second integrated circuit; and coupling an external component to the double side molded interposer unit.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventors: Joungin Yang, Dongjin Jung, In Sang Yoon
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Patent number: 7482203Abstract: A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first top molding compound to cover the first electrical interconnects and a portion of the top side of the first substrate, and encapsulating a first bottom molding compound to cover the first integrated circuit and a bottom side the first substrate, and stacking a second device, having a second integrated circuit package, below the first device with a second top molding compound of the second device providing a space between the first device and the second device, wherein the second device includes the second top molding compound and a second bottom molding compound in a similar manner to the first device.Type: GrantFiled: December 26, 2007Date of Patent: January 27, 2009Assignee: Stats Chippac Ltd.Inventors: Sungmin Song, Choong Bin Yim, SeongMin Lee, Jaehyun Lim, Joungin Yang, DongSam Park
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Publication number: 20090001540Abstract: A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical contact with the first semiconductor die through a first adhesive, such as a film on wire adhesive. A second DSM ISM is in physical contact with the first DSM ISM through a second adhesive. The arrangement of the first and second DSM ISM reduce headroom requirements for the package and increase device packing density. Each DSM ISM has semiconductor die disposed in cavities. An interposer is disposed above the top DSM ISM. Wire bonds connect the semiconductor die and DSM ISMs to the solder balls. An encapsulant surrounds the first semiconductor die and first DSM ISM with an exposed mold area in the encapsulant above the interposer.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: STATS CHIPPAC, LTD.Inventors: JoungIn YANG, ChoongBin YIM, KeonTeak KANG, YoungChul KIM
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Publication number: 20080105965Abstract: A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first top molding compound to cover the first electrical interconnects and a portion of the top side of the first substrate, and encapsulating a first bottom molding compound to cover the first integrated circuit and a bottom side the first substrate, and stacking a second device, having a second integrated circuit package, below the first device with a second top molding compound of the second device providing a space between the first device and the second device, wherein the second device includes the second top molding compound and a second bottom molding compound in a similar manner to the first device.Type: ApplicationFiled: December 26, 2007Publication date: May 8, 2008Applicant: STATS ChipPAC Ltd.Inventors: Sungmin Song, Choong Bin Yim, Seongmin Lee, Jaehyun Lim, Joungin Yang, Dongsam Park
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Patent number: 7312519Abstract: A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first top molding compound to cover the first electrical interconnects and a portion of the top side of the first substrate, and encapsulating a first bottom molding compound to cover the first integrated circuit and a bottom side the first substrate, and stacking a second device, having a second integrated circuit package, below the first device with a second top molding compound of the second device providing a space between the first device and the second device, wherein the second device includes the second top molding compound and a second bottom molding compound in a similar manner to the first device.Type: GrantFiled: January 12, 2006Date of Patent: December 25, 2007Assignee: Stats Chippac Ltd.Inventors: Sungmin Song, Choong Bin Yim, Seongmin Lee, Jaehyun Lim, Joungin Yang, Dongsam Park
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Patent number: 7298037Abstract: A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a substrate with the recess positioned therebetween, and attaching a first electrical interconnect extending from the recess and connected between the integrated circuit die and the substrate.Type: GrantFiled: February 17, 2006Date of Patent: November 20, 2007Assignee: Stats Chippac Ltd.Inventors: Choong Bin Yim, Sungmin Song, SeongMin Lee, Jaehyun Lim, Joungin Yang, DongSam Park
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Publication number: 20070194423Abstract: A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a substrate with the recess positioned therebetween, and attaching a first electrical interconnect extending from the recess and connected between the integrated circuit die and the substrate.Type: ApplicationFiled: February 17, 2006Publication date: August 23, 2007Applicant: STATS CHIPPAC LTD.Inventors: Choong Bin Yim, Sungmin Song, SeongMin Lee, Jaehyun Lim, Joungin Yang, DongSam Park
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Publication number: 20070158810Abstract: A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first top molding compound to cover the first electrical interconnects and a portion of the top side of the first substrate, and encapsulating a first bottom molding compound to cover the first integrated circuit and a bottom side the first substrate, and stacking a second device, having a second integrated circuit package, below the first device with a second top molding compound of the second device providing a space between the first device and the second device, wherein the second device includes the second top molding compound and a second bottom molding compound in a similar manner to the first device.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Applicant: STATS ChipPAC Ltd.Inventors: Sungmin Song, Choong Yim, Seongmin Lee, Jaehyun Lim, Joungin Yang, Dongsam Park