Patents by Inventor Joy Cheng

Joy Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741410
    Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a metal complex including a radical generator, an organic core, and an organic solvent. By way of example, the organic core includes at least one cross-linker site. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang
  • Publication number: 20200152468
    Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.
    Type: Application
    Filed: December 23, 2019
    Publication date: May 14, 2020
    Inventors: Chien-Wei Wang, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20200135452
    Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.
    Type: Application
    Filed: December 31, 2019
    Publication date: April 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han KO, Joy CHENG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Patent number: 10635000
    Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10622211
    Abstract: A wafer is rinsed with a solvent. The wafer has an increased hydrophobicity as a result of being rinsed with the solvent. A metal-containing material is formed over the wafer after the wafer has been rinsed with the solvent. One or more lithography processes are performed at least in part using the metal-containing material. The metal-containing material is removed during or after the performing of the one or more lithography processes. The increased hydrophobicity of the wafer facilitates a removal of the metal-containing material.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang
  • Publication number: 20200062883
    Abstract: A polymer composition and a process for the production of this composition comprising a base resin is disclosed herein. The base resin includes a very high molecular weight component, a low molecular weight component, and a high molecular weight component having a weight average molecular weight higher than the weight average molecular weight of the low molecular weight component but lower than the weight average molecular weight of the very high molecular weight component. An amount of the very high molecular weight component in the base resin is 0.5 to 8 wt %. The very high molecular weight component has a viscosity average molecular weight of greater than 1100 kg/mol. The composition has FRR21/5 of equal to or greater than 38, a melt flow rate MFR21 of equal to or greater than 6.5 g/10 min and a viscosity at a shear stress of 747 Pa (eta747) of 450 to 3000 kPas.
    Type: Application
    Filed: November 15, 2017
    Publication date: February 27, 2020
    Inventors: Peter Roos, Joy Cheng, Mark Jeruzal, Qizheng Duo, Erik Eriksson
  • Patent number: 10573519
    Abstract: A method for performing a photolithography process is provided. The method includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed region and an unexposed region by performing an exposure process. The method includes performing a baking process on the resist layer, so that voids are formed in the exposed region of the resist layer. The method also includes removing the unexposed region of the resist layer to form a recess in the resist layer and filling a post treatment coating material in the recess and the void. The method further includes removing a portion of the post treatment coating material by performing a second develop process, and another portion of the post treatment coating material is left on surfaces of the exposed region of the resist layer to form a patterned resist layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Ko, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10515812
    Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution, and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20190384173
    Abstract: A photoresist layer is formed over a wafer. The photoresist layer includes a metallic photoresist material and one or more additives. An extreme ultraviolet (EUV) lithography process is performed using the photoresist layer. The one or more additives include: a solvent having a boiling point greater than about 150 degrees Celsius, a photo acid generator, a photo base generator, a quencher, a photo de-composed base, a thermal acid generator, or a photo sensitivity cross-linker.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang
  • Patent number: 10418245
    Abstract: A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Jie Lee, Joy Cheng
  • Publication number: 20190164746
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed. A surface grafting layer is formed on the underlying structure. A photo resist layer is formed on the surface grafting layer. The surface grafting layer includes a coating material including a backbone polymer, a surface grafting unit coupled to the backbone polymer and an adhesion unit coupled to the backbone polymer.
    Type: Application
    Filed: February 26, 2018
    Publication date: May 30, 2019
    Inventors: Yu-Ling Chang CHIEN, Chien-Chih CHEN, Chin-Hsiang LIN, Ching-Yu CHANG, Joy CHENG
  • Publication number: 20190146342
    Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate, and selectively exposing the photoresist layer to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer, and the protective layer is removed. The protective layer includes a polymer having fluorocarbon pendant groups.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 16, 2019
    Inventors: An-Ren ZI, Chin-Hsiang LIN, Ching-Yu CHANG, Joy CHENG
  • Publication number: 20190146337
    Abstract: A photoresist developer includes a solvent having Hansen solubility parameters of 25<?d<15, 25<?p<10, and 30<?p<6; an acid having an acid dissociation constant, pKa, of ?15<pKa<4, or a base having a pKa of 40>pKa>9.5; and a chelate.
    Type: Application
    Filed: March 28, 2018
    Publication date: May 16, 2019
    Inventors: An-Ren ZI, Chin-Hsiang LIN, Ching-Yu CHANG, Joy CHENG
  • Patent number: 10274847
    Abstract: A photo-sensitive layer is applied over a wafer. The photo-sensitive layer is exposed. In some embodiments, the photo-sensitive layer is exposed to EUV light. The photo-sensitive layer is baked. The photo-sensitive layer is developed. Humidity is introduced in at least one of: the applying, the baking, or the developing.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang, Joy Cheng
  • Patent number: 10259907
    Abstract: The present invention relates to a novel block copolymer of structure 1, wherein, A- is a block polymer chain, B is a block polymer chain, wherein, A- and B- are chemically different, covalently connected polymer chains, which are phase separable and the moiety X(Y(Z)b)a is a junction group, which comprises a surface active pendant moiety Y(Z)b wherein: a is an integer from 1 to 4 denoting the number of surface active pendant moieties Y(Z)b on X, b is an integer from 1 to 5 denoting the number of Z moieties on the linking moiety Y, X is a linking group between the A polymer block, the B polymer block and the moiety Y, Y is a linking group or a direct valence bond between X and Z; and Z is a moiety independently selected from, a fluorine containing moiety, a Si1-Si8 siloxane containing moiety or a hydrocarbon moiety with at least 18 carbons, and further wherein the junction group X(Y(Z)b)a has a surface energy less than that that of the block A and less than that of the block B.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: April 16, 2019
    Assignees: AZ Electronic Materials (Luxembourg) S.à r.l., IBM Corporation
    Inventors: Ankit Vora, Eri Hirahara, Joy Cheng, Durairaj Baskaran, Orest Polishchuk, Melia Tjio, Margareta Paunescu, Daniel Sanders, Guanyang Lin
  • Publication number: 20190094716
    Abstract: A photo-sensitive layer is applied over a wafer. The photo-sensitive layer is exposed. In some embodiments, the photo-sensitive layer is exposed to EUV light. The photo-sensitive layer is baked. The photo-sensitive layer is developed. Humidity is introduced in at least one of: the applying, the baking, or the developing.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang, Joy Cheng
  • Publication number: 20190086818
    Abstract: A photo-sensitive layer is applied over a wafer. The photo-sensitive layer is exposed. In some embodiments, the photo-sensitive layer is exposed to EUV light. The photo-sensitive layer is baked. The photo-sensitive layer is developed. Humidity is introduced in at least one of: the applying, the baking, or the developing.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 21, 2019
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang, Joy Cheng
  • Publication number: 20190080901
    Abstract: A method for performing a photolithography process is provided. The method includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed region and an unexposed region by performing an exposure process. The method includes performing a baking process on the resist layer, so that voids are formed in the exposed region of the resist layer. The method also includes removing the unexposed region of the resist layer to form a recess in the resist layer and filling a post treatment coating material in the recess and the void. The method further includes removing a portion of the post treatment coating material by performing a second develop process, and another portion of the post treatment coating material is left on surfaces of the exposed region of the resist layer to form a patterned resist layer.
    Type: Application
    Filed: February 27, 2018
    Publication date: March 14, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han KO, Joy CHENG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20190067002
    Abstract: In a method of manufacturing a semiconductor device, a photo resist layer is formed over a substrate with underlying structures. The first photo resist layer is exposed to exposure radiation. The exposed first photo resist layer is developed with a developing solution. A planarization layer is formed over the developed photo resist layer. The underlying structures include concave portions, and a part of the concave portions is not filled by the developed first photo resist.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 28, 2019
    Inventors: Yu-Chung SU, Joy CHENG, Ching-Yu CHANG
  • Publication number: 20190064669
    Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.
    Type: Application
    Filed: September 10, 2018
    Publication date: February 28, 2019
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin