Abstract: Systems, methods, and non-transitory computer-readable media can determine at least one request to access a content item, wherein the requested content item was composed using a set of camera feeds that capture one or more scenes from a set of different positions. Information describing an automated viewing mode for navigating at least some of the scenes in the requested content item is obtained. A viewport interface is provided on a display screen of the computing device through which playback of the requested content item is presented. The viewport interface is automatically navigated through at least some of the scenes during playback of the requested content item based at least in part on the automated viewing mode.

Abstract: A camera system is configured to capture 360 degree image information of a local area, at least a portion of which is in stereo. The camera system includes a plurality of peripheral cameras, a plurality of axis cameras, a first rigid plate, and a second rigid plate, each aligned along an alignment axis. The peripheral cameras are arranged in a ring configuration that allows objects in the local area past a threshold distance to be within the fields of view of at least two peripheral cameras. The first and second rigid plates secure to a top and a bottom surface of the ring of peripheral cameras, respectively. At least one axis camera is arranged along the alignment axis and is coupled perpendicularly to a surface of the first rigid plate.

Abstract: A camera calibration system jointly calibrates multiple cameras in a camera rig system. The camera calibration system obtains configuration information about the multiple cameras in the camera rig system, such as position and orientation for each camera relative to other cameras. The camera calibration system estimates calibration parameters (e.g., rotation and translation) for the multiple cameras based on the obtained configuration information. The camera calibration system receives 2D images of a test object captured by the multiple cameras and obtains known information about the test object such as location, size, texture and detailed information of visually distinguishable points of the test object. The camera calibration system then generates a 3D model of the test object based on the received 2D images and the estimated calibration parameters. The generated 3D model is evaluated in comparison with the actual test object to determine a calibration error.

Abstract: Systems, methods, and non-transitory computer-readable media can determine at least one request to access a content item, wherein the content item was composed using a set of camera feeds that capture at least one scene from a set of different positions. A viewport interface can be provided on a display screen of the computing device through which playback of the content item is presented, the viewport interface being configured to allow a user operating the computing device to virtually navigate the at least one scene by changing i) a direction of the viewport interface relative to the scene or ii) a zoom level of the viewport interface. A navigation indicator can be provided in the viewport interface, the navigation indicator being configured to visually indicate any changes to a respective direction and zoom level of the viewport interface during playback of the content item.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the viva is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the viva is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder bail attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: A system and method for packaging a semiconductor chip, the system comprising a semiconductor chip having a contact point, a top surface, and a bottom surface; a housing which encapsulates the top surface of the semiconductor chip wherein the bottom surface is unencapsulated; a pin having a top member encapsulated inside the housing and a protruding member extending outside the housing, the pin providing a conduit through which an electrical charge may travel; a bond wire electrically connected to the pin to the contact point on the semiconductor chip to provide an electrical path from the pin to the semiconductor chip; and a fixture having a matrix of cavities for receiving and supporting the protruding member of the pin during packaging. The system and method result in a packaged semiconductor device which is cost effective, results in smaller package dimensions, and reduces tooling lead-time and manufacturing costs.

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: A system (10) for coupling conductive pellets (40) to a component (12) of an integrated circuit has a substantially planar ribbon (14) that includes a conductive material. A punching apparatus (16) and (38) penetrates the ribbon (14) to form the conductive pellets (40). The punching apparatus (16) and (38) also moves relative to the component (12) to the conductive pellets (40) to the component (12).