Patents by Inventor Jo Young Park
Jo Young Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162113Abstract: In one example, an electronic device comprises a substrate comprising a conductive structure and an inner side and an outer side, a first electronic component over the inner side of the substrate and coupled with the conductive structure, a lid over the substrate and the first electronic component and comprising a first hole in the lid, and a thermal interface material between the first electronic component and the lid. The thermal interface material is in the first hole. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: November 11, 2022Publication date: May 16, 2024Applicants: Amkor Technology Singapore Holding Pte. Ltd., Amkor Technology Singapore Holding Pte. Ltd.Inventors: Dong Hyeon Park, Yun Ah Kim, Seok Ho Na, Won Ho Choi, Dong Su Ryu, Jo Hyun Bae, Min Jae Kong, Jin Young Khim, Jae Yeong Bae, Dong Hee Kang
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Patent number: 11309326Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: GrantFiled: March 27, 2020Date of Patent: April 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Publication number: 20200227430Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: 10658374Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: GrantFiled: May 20, 2019Date of Patent: May 19, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Publication number: 20190279999Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: ApplicationFiled: May 20, 2019Publication date: September 12, 2019Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: 10297543Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: GrantFiled: June 13, 2017Date of Patent: May 21, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Publication number: 20180166380Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: ApplicationFiled: June 13, 2017Publication date: June 14, 2018Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: 9670480Abstract: A method comprising transforming Schizosaccharomyces pombe with a deletion cassette, constructed by four-round serial PCR, block PCR or total gene synthesis, containing a homologous recombination site is provided for preparing gene-targeted heterozygous deletion Schizosaccharomyces pombe. Also provided are gene-targeted hetero2ygous deletion Schizosaccharomyces pombe mutants prepared by the method, and a library of gene-targeted heterozygous deletion Schizosaccharomyces pombe mutants. Further, the library is useful in constructing a method and a kit for screening a drug's modes of action.Type: GrantFiled: August 27, 2008Date of Patent: June 6, 2017Assignee: Korea Research Institute of Bioscience and BiotechnologyInventors: Kwang Lae Hoe, Dong Uk Kim, Mi Sun Won, Hyang Sook Yoo, Dong Sup Kim, Han Oh Park, Kyung Sook Chung, Young Joo Jang, Mi Young Nam, Sang Jo Han, Shin Jung Choi, Seung Tae Baek, Hyong Bai Kim, Kyung Sun Heo, Hye Mi Lee, Min Ho Lee, Jo Young Park
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Publication number: 20110190163Abstract: A method comprising transforming Schizosaccharomyces pombe with a deletion cassette, constructed by four-round serial PCR, block PCR or total gene synthesis, containing a homologous recombination site is provided for preparing gene-targeted heterozygous deletion Schizosaccharomyces pombe. Also provided are gene-targeted hetero2ygous deletion Schizosaccharomyces pombe mutants prepared by the method, and a library of gene-targeted heterozygous deletion Schizosaccharomyces pombe mutants. Further, the library is useful in constructing a method and a kit for screening a drug's modes of action.Type: ApplicationFiled: August 27, 2008Publication date: August 4, 2011Applicant: Korea Research Institute of Bioscience and BiotechnologyInventors: Kwang Lae Hoe, Dong Uk Kim, Mi Sun Won, Hyang Sook Yoo, Dong Sup Kim, Han Oh Park, Kyung Sook Chung, Young Joo Jang, Mi Young Nam, Sang Jo Han, Hin Jung Choi, Seung Tae Baek, Hyong Bai Kim, Kyung Sun Heo, Hye Mi Lee, Min Ho Lee, Jo Young Park