Patents by Inventor Jozef Louis Van Meerbergen

Jozef Louis Van Meerbergen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8312160
    Abstract: A sensor device includes at least one autonomous streaming module. Predetermined internal events of the autonomous streaming module or predetermined external events from streaming data at an interface to a smart shell of the autonomous streaming module are detected. An operational mode of a component or subsystem within the smart shell of the autonomous streaming module is controlled in response to the detection.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: November 13, 2012
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jozef Louis Van Meerbergen, Anteneh Alemu Abbo, Martinus Theodorus Bennebroek, Octavio Santana, Lennart Yseboodt
  • Publication number: 20100293288
    Abstract: The present invention relates to a sensor device or sensor node and a method of controlling operation of the sensor device, wherein the sensor device comprises at least one autonomous streaming module and wherein predetermined internal events of the autonomous streaming module or predetermined external events from streaming data at an interface to a smart shell of the autonomous streaming module are detected, and an operational mode of a component or subsystem within the smart shell of the autonomous streaming module is controlled in response to the detection.
    Type: Application
    Filed: January 26, 2009
    Publication date: November 18, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Jozef Louis Van Meerbergen, Anteneh Alemu Abbo, Martinus Theodorus Bennebroek, Octavio Santana, Lennart Yseboodt
  • Patent number: 7113554
    Abstract: A turbo decoder system (1) for decoding turbo coded bits, is provided with a system input (2) and a plurality of turbo decoders (3; 3-1, . . . 3-n) each having a turbo decoder input (4; 4-1, . . . 4-n). The plurality of turbo decoders (3; 3-1, . . . 3-n) is arranged in parallel, and the system (1) is further provided with an allocating device (6) coupled between the system input (2) and the turbo decoder inputs (4; 4-1, . . . 4-n) for dynamically allocating the turbo coded bits to one of the turbo decoders (3; 3-1, . . . 3n).
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: September 26, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Johannus Theodorus Matheus Hubertus Dielissen, Josephus Antonius Huisken, Jozef Louis Van Meerbergen
  • Patent number: 6643738
    Abstract: A data processor has a cache memory with an associative memory for storing at least a first and second groups of associations between a respective main memory addresses and cache memory locations. At least one cache memory location is dynamically assignable to different ones of the groups for use in associations of the assigned group. When an instruction indicates a main memory address a group is selected group for finding the cache memory location associated with the main memory address. In an embodiment, the processor accesses streams of addresses from iteratively computed main memory addresses. Each stream has its own group of associations of addresses from the stream with cache memory locations assigned to that group. The remaining cache memory locations are accessed with set associative mapping. Thus, cache memory locations can be assigned to different streams on an “as needed” basis and the remaining cache memory locations can be used for non-stream addresses.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: November 4, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Adwin Hugo Timmer, Françoise Jeannette Harmsze, Jeroen Anton Johan Leijten, Jozef Louis Van Meerbergen
  • Publication number: 20020136332
    Abstract: A turbo decoder system (1) for decoding turbo coded bits, is provided with a system input (2) and a plurality of turbo decoders (3; 3-1, . . . 3-n) each having a turbo decoder input (4; 4-1, . . . 4-n). The plurality of turbo decoders (3; 3-1, . . . 3-n) is arranged in parallel, and the system (1) is further provided with an allocating device (6) coupled between the system input (2) and the turbo decoder inputs (4; 4-1, . . . 4-n) for dynamically allocating the turbo coded bits to one of the turbo decoders (3; 3-1, . . . 3-n).
    Type: Application
    Filed: February 19, 2002
    Publication date: September 26, 2002
    Inventors: Johannus Theodorus Matheus Hubertus Dielissen, Josephus Antonius Huisken, Jozef Louis Van Meerbergen
  • Publication number: 20020009001
    Abstract: An integrated circuit has a matrix of programmable cells. Programmable switches connect pairs of neighboring cells. Each cell contains a local conductor connecting a pair of the switches on opposite sides of the cell. Each switch connects the local conductors of the neighboring cells. At least one of the cells have a computation logic circuit having either an input connected to the local conductor of the at least one of the cells. The computation logic circuit has programmably individually activatable outputs connected to the local conductors of neighbor cells of the at least one of the cells or an output connected to the local conductor of the at least one of the cells and programmably individually activatable inputs connected to the local conductors of neighbor cells of the at least one of the cells.
    Type: Application
    Filed: May 30, 2001
    Publication date: January 24, 2002
    Inventors: Jean-Paul Theis, Katarzyna Leijten-Nowak, Jozef Louis Van Meerbergen
  • Publication number: 20020004876
    Abstract: A data processor has a cache memory with an associative memory for storing at least a first and second groups of associations between a respective main memory addresses and cache memory locations. At least one cache memory location is dynamically assignable to different ones of the groups for use in associations of the assigned group. When an instruction indicates a main memory address a group is selected group for finding the cache memory location associated with the main memory address. In an embodiment, the processor accesses streams of addresses from iteratively computed main memory addresses. Each stream has its own group of associations of addresses from the stream with cache memory locations assigned to that group. The remaining cache memory locations are accessed with set associative mapping. Thus, cache memory locations can be assigned to different streams on an “as needed” basis and the remaining cache memory locations can be used for non-stream addresses.
    Type: Application
    Filed: December 12, 2000
    Publication date: January 10, 2002
    Applicant: FEE COMPUTATION
    Inventors: Adwin Hugo Timmer, Francoise Jeannette Harmsze, Jeroen Anton Johan Leijten, Jozef Louis Van Meerbergen