Abstract: Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor.

Abstract: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

Abstract: A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.

Abstract: Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed within the well regions according to the selected threshold voltage. First and second gate structures are formed over the first and second well regions having varied channel lengths. A first source region is formed in the first back gate region and a first drain region is formed in the first drain extension region. A second source region is formed in the second back gate region and a second drain region is formed in the drain extension region.

Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.

Abstract: An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown voltage is, at least partially, increased by forming a p-doped region (140) within a semiconductor substrate (102), and forming a drain region (166) of the OTP EPROM (100) within the p-doped region (140).

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region (220) is formed in the bulk substrate (210). A first active region (220) is formed in the first lightly doped region (220). A second lightly doped region (320) is formed in the bulk substrate (310). A second active region (340) is formed in the second lightly doped region (320). A third active region (340) is formed in the bulk substrate (310). An oxide layer (230, 330) is disposed outwardly from the bulk substrate (210, 310) and a floating gate layer (250, 350) is disposed outwardly from the oxide layer (230, 330).

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wherein the floating gate (230) has a metal control gate (250) located thereover. The semiconductor device (200), in the same embodiment, further includes a dielectric layer (240) located between the floating gate 230 and the metal control gate (250), the dielectric layer (240) having a gettering material located therein.

Abstract: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

Abstract: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

Abstract: The present invention facilitates semiconductor fabrication by maintaining uniform thickness of a gate oxide layer (112) during the oxide growth process of non-volatile memory devices (100). The uniform thickness of a gate oxide layer (112) is obtained by defining the boundaries of the source and drain areas (110) of a memory device (100) with the source/drain dopant masking and implanting operation. If an isolation barrier (108) is present it is kept a minimum safe distance (130) away from the periphery of the conductive gate layer (114) to avoid birds-beak regions (30) responsible for non-uniform gate oxide growth. As a result, the corresponding charge losses and weak cells are mitigated, thereby facilitating the fabrication of more reliable memory cells (100). Because a more uniform gate oxide thickness (112) is used in association with the memory cells (100), a single significantly thinner gate oxide layer (114) may be employed throughout the memory device (100).

Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.

Abstract: An EEPROM memory cell uses PMOS type floating gate transistor formed in a n-well, where the floating gate is routed over a p? diffused region formed in the n-well to form a control capacitor. The PMOS floating gate transistor uses a p-type diffused region below the p+ active region forming the drain to provide a higher breakdown voltage. Cell programming can be performed through hot-electron injection, with the electric field across the control capacitor to aid injection into the floating gate. FN erasure is achieved by taking the potential of the n-well to the programming voltage while holding the potential of the control capacitor at a low voltage.