Abstract: For the laser drilling of organic materials, in particular for making blind holes in dielectric layers, a frequency-doubled Nd-vanadate laser with the following parameters is used: pulse width <40 ns pulse frequency ?20 kHz wavelength =532 nm.

Abstract: The invention relates to an intermediate support for electronic components, for example a semiconductor, comprising a plastic substrate with contact bumps (2) in one-piece, covered with a metallic layer, which is electrically connected to at least one conducting path of said substrate (1). Said contact bumps (2) each comprise a well wettable path, extending from the tips to the base thereof and each leading to the corresponding contact bump (2) base in a solder receiving region with suction (11). Therefore, by soldering said contact bumps, excess solder can be sucked off, such that short circuits can be avoided even without the use of a solder resist. By solder contacting said intermediate support, the solder can thus be applied over a large surface on a circuit support and sucked off the cavities between the contact points by reflow soldering.

Abstract: A method and device for the laser drilling of laminates includes the use of a frequency-doubled Nd vanadate laser. The laser includes the following parameters: pulse width<40 ns, pulse frequency≧30 kHz for the metal layer and ≧20 kHz for the dielectric layer, and wavelength=532 nmn. Such a laser is used for the laser drilling of laminates which have at least one metal layer and at least one dielectric layer including an organic material.

Abstract: According to the invention, the connection side of an undivided semiconductor wafer (1) is directly connected to a thermoplastic film (2), whose thermal expansion coefficient is approximately as low as that of the semiconductor material. Protuberance (21) are moulded onto the exposed underside of the film (2) by a hot embossing process, said protuberances acting as elastic external connections (25) and being connected in a conductive manner to internal connections (24) or to the wafer terminal elements (11) via passages (22). Individual semiconductor modules or packages that can be contacted on a printed circuit board by means of the plastic protuberances (21) are produced by dividing the finished contacted wafer.

Abstract: A method for producing printed circuit boards having coarse conductor structures and at least one region having fine conductor structures. The coarse conductor structures and the fine conductor structures are etched out of a metal layer in a common etching process. An etching resist patterned by means of photolithography is used in the region of the coarse conductor structures, and an etching resist patterned with the aid of a laser beam is used in the region of the fine conductor structures.

Abstract: A metal layer, an etching resist and a photoresist are successively applied to an electrically insulating substrate. Whereupon the photoresist is patterned by photolithography in such a way that it covers a pattern of the later coarse conductor structures and the entire region of the later fine conductor structures. After the uncovered etching resist has been stripped, the photoresist is removed, whereupon the etching resist is patterned with the aid of a laser beam in such a way that it has the pattern of the fine conductor structures. The coarse conductor structures and the fine conductor structures are then formed in a common etching process.

Abstract: The invention relates to a method for producing interconnections with electrically conductive cross connections between the top and the bottom part of a substrate and interconnections having such cross connections. The substrate (S1) is given a slanted, roof-shaped or convex contour (K1) in the area of at least one front face and/or in the area of at least one inner wall of a recess. After metallizing the substrate (S1), printed-board conductor-shaped cross connections (Q) are produced in the area of the above-mentioned contours (K1) simultaneously with laser structuring of printed board conductors (L) on the top part (0) and the bottom part (U) of the substrate (S1).

Abstract: A interconnection circuit includes a dielectric plane having conductors fabricated from copper disposed on each side of the dielectric plane. An opening known as a via disposed through the dielectric plane includes a conductive link between the conductors disposed on either side of the dielectric plane. The conductive link includes a first layer fabricated from copper and a second layer of Nickel disposed over the copper layer to strengthen the first layer and prevent fractures known as barrel cracks in the conductive link. A third layer composed of Gold is deposited over the second layer to protect the second layer of Nickel from corrosion. In another embodiment of the subject invention the third layer is composed of an easily cleaned or removed metal and a coating of Gold is deposited in specific discrete locations to facilitate wire bonding or soldering.

Abstract: A metal layer, an etching resist and a photoresist are successively applied to an electrically insulating substrate. Whereupon the photoresist is patterned by photolithography in such a way that it covers a pattern of the later coarse conductor structures and the entire region of the later fine conductor structures. After the uncovered etching resist has been stripped, the photoresist is removed, whereupon the etching resist is patterned with the aid of a laser beam in such a way that it has the pattern of the fine conductor structures. The coarse conductor structures and the fine conductor structures are then formed in a common etching process.

Abstract: An intermediate support which supports a semiconductor module on a printed circuit board has, on its underside, contact studs which are integrally formed from plastic and are intended for the contact-connection to the printed circuit board. The support is also provided with supporting studs which are preferably arranged in a comer region and are connected to the printed circuit board to improve the thermomechanical reliability of the semiconductor module.

Abstract: A first wiring layer and metallized plated-through holes are formed in/on a substrate. A substrate layer is then applied to the top of the substrate by injection molding, during which an injected material passes through the plated-through holes, resulting in polymer studs being produced on an underside of the substrate. A second wiring layer, formed on the substrate layer, is electrically conductively connected to the first wiring layer by blind plated-through holes, and hence to external connections on the polymer studs by the plated-through holes.

Abstract: A structural shape has an injection molded, three-dimensional substrate composed of an electrically insulating polymer, polymer studs planarly arranged on the underside of the substrate and co-formed during injection molding, outside terminals formed on the polymer studs by a solderable end surface, interconnections fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals, and at least one chip arranged on the substrate and whose terminals are electrically conductively connected to the inside terminals. The structural shape is suitable for single, few or multi chip module and unites the advantages of a ball grid array with the advantages of MID technology (Molded Interconnection Devices). The manufacture and metallization of the polymer studs can take place with minimal additional outlay in the framework of the method steps already required in the MID technology.

Abstract: The output of a continuously pumped, Q-switched, Nd:YAG laser (10) is frequency converted to provide ultraviolet light (62) for forming vias (72, 74) in targets (40) having metallic layers (64,68) and a dielectric layer (66). The invention employs a first laser output of high power density to ablate the metallic layer and a second laser output of a lower power density to ablate the dielectric layer. The parameters of the output pulses (62) are selected to facilitate substantially clean, sequential drilling or via formation. These parameters typically include at least two of the following criteria: power density first above and then below the ablation threshold of the conductor, wavelength less than 400 nm, a temporal pulse width shorter than about 100 nanoseconds, and a repetition rate of greater than about one kilohertz.