Abstract: A low-delay hybrid noise reduction system includes a reference audio receiving device, an error audio receiving device, an audio output device, and an audio processing device. The audio processing device includes a feedforward noise reduction filter module, a feedback noise reduction filter module, and a mixer. The feedforward noise reduction filter module includes a feedforward least mean squares (LMS) filter, a low-stage finite impulse response (FIR) filter, and 1st to Nth-stage biquad filters. The 1st to Nth-stage biquad filters is set on the input end of the low-stage finite impulse response filter to perform low-delay filtering on the reference source audio signal received and outputs to the low-stage FIR filter so as to output the feedforward noise reduction signal through the low-stage FIR filter.

Abstract: A low-delay hybrid noise reduction system includes a reference audio receiving device, an error audio receiving device, an audio output device, and an audio processing device. The audio processing device includes a feedforward noise reduction filter module, a feedback noise reduction filter module, and a mixer. The feedforward noise reduction filter module includes a feedforward least mean squares (LMS) filter, a low-stage finite impulse response (FIR) filter, and 1st to Nth-stage biquad filters. The 1st to Nth-stage biquad filters is set on the input end of the low-stage finite impulse response filter to perform low-delay filtering on the reference source audio signal received and outputs to the low-stage FIR filter so as to output the feedforward noise reduction signal through the low-stage FIR filter.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

Abstract: The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.