Abstract: A synchronization pattern is provided within an incoming waveform which represents a serial data stream transmitted at a rate determined by a data clock. The synchronization pattern includes a periodic training portion and a sync word portion. The periodic training portion is periodic and has a preselected period. As the periodic training portion is received, a receiver clock phase-locks to the periodic training portion of the incoming waveform, and a sampling circuit periodically samples the incoming waveform relative to the phase and frequency of the receiver clock to produce sample words. Thereafter, a subset of the sample words are selected utilizing a selection pattern having a period equal to the period of the periodic training portion of the incoming waveform. Utilizing the selected subset of sample words, a sync indicator word is produced and compared to preselected criteria. Such a sync indicator word may be produced with reference to the sign of each sample word of the subset of sample words.

Abstract: An error correcting scheme for processing data which is transmitted on a broadband and/or CATV network and utilizes the IEEE 802.4 three-level duobinary AM/PSK (phase shift keying) coding format. The error correcting scheme utilizes two thresholders. One of the thresholders makes data (1 or 0) decisions while the other thresholder makes non-data or no non-data (non-data) decisions. Pattern matching and windowing are used to detect non-data symbols which are corrected if the non-data symbols deviate from a predetermined pattern. The template used in the pattern matching is determined from the state of a demodulator.

Abstract: A protection circuit is provided in which the output voltage is sensed and the output device is shut-off for protection when the output voltage falls below a predetermined trip voltage. The monolithic integrated circuit includes a voltage shifting circuit for transferring the output voltage to a biasing circuit which biases a switching circuit which turns the line driver off, when an overload or short circuit causes a voltage drop below a predetermined trip voltage. The protection circuit is disabled during start-up or signal rise time by splitting the input signal into two separate paths in which the signals have different delays. The shorter delay allowing the input signal to rise and to appear on the output line before the longer delay input signal rises enabling the protection circuit.

Abstract: An improved clock retiming system for pulse coded data is provided in which the clock signals are extracted from the encoded data and first and second signals of the same amplitude and frequency but of different phase are generated from the clock signals. First and second amplifiers having variable gains provide amplification for the first and second signals, respectively. The first and second amplified signals are summed to produce a third signal having a phase which is a function of the relative amplitudes of the first and second amplified signals. The original pulse encoded data is sampled with the third signal to produce the retimed data output. The original pulse encoded data is also utilized to sample the third signal. The resulting signal is filtered to provide a DC voltage feedback error signal indicative of the phase difference between the third signal and the original pulse encoded data.